This is a squash of several imx_v6_v7_defconfig update patches.
- Enable tlv320aic3x audio codec by default (Phytec PBAB01 board)
- Enable DS1307 rtc and gpio fan by default (TBS2910 board)
- Select thermal related drivers
- Add SNVS power off driver
Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
Signed-off-by: Soeren Moch <smoch@web.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently the kernel patches all necessary instructions once at boot
time, so modules are not covered by this.
Change the apply_alternatives() function to take a beginning and an
end pointer and introduce a new variant (apply_alternatives_all()) to
cover the existing use case for the static kernel image section.
Add a module_finalize() function to arm64 to check for an
alternatives section in a module and patch only the instructions from
that specific area.
Since that module code is not touched before the module
initialization has ended, we don't need to halt the machine before
doing the patching in the module's code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
If the overflow threshold for a counter is set above or near the
0xffffffff boundary then the kernel may lose track of the overflow
causing only events that occur *after* the overflow to be recorded.
Specifically the problem occurs when the value of the performance counter
overtakes its original programmed value due to wrap around.
Typical solutions to this problem are either to avoid programming in
values likely to be overtaken or to treat the overflow bit as the 33rd
bit of the counter.
Its somewhat fiddly to refactor the code to correctly handle the 33rd bit
during irqsave sections (context switches for example) so instead we take
the simpler approach of avoiding values likely to be overtaken.
We set the limit to half of max_period because this matches the limit
imposed in __hw_perf_event_init(). This causes a doubling of the interrupt
rate for large threshold values, however even with a very fast counter
ticking at 4GHz the interrupt rate would only be ~1Hz.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
If I include asm/irq.h on the top of my code, and set ARCH=arm64,
I'll get a compile warning, details are below:
warning: ‘struct pt_regs’
declared inside parameter list [enabled by default]
This patch is suggested by Arnd, see:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-December/308270.html
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Building arm64.allmodconfig leads to the following warning:
usb/gadget/function/f_ncm.c:203:0: warning: "NCAPS" redefined
#define NCAPS (USB_CDC_NCM_NCAP_ETH_FILTER | USB_CDC_NCM_NCAP_CRC_MODE)
^
In file included from /home/build/work/batch/arch/arm64/include/asm/io.h:32:0,
from /home/build/work/batch/include/linux/clocksource.h:19,
from /home/build/work/batch/include/clocksource/arm_arch_timer.h:19,
from /home/build/work/batch/arch/arm64/include/asm/arch_timer.h:27,
from /home/build/work/batch/arch/arm64/include/asm/timex.h:19,
from /home/build/work/batch/include/linux/timex.h:65,
from /home/build/work/batch/include/linux/sched.h:19,
from /home/build/work/batch/arch/arm64/include/asm/compat.h:25,
from /home/build/work/batch/arch/arm64/include/asm/stat.h:23,
from /home/build/work/batch/include/linux/stat.h:5,
from /home/build/work/batch/include/linux/module.h:10,
from /home/build/work/batch/drivers/usb/gadget/function/f_ncm.c:19:
arch/arm64/include/asm/cpufeature.h:27:0: note: this is the location of the previous definition
#define NCAPS 2
So add a ARM64 prefix to avoid such problem.
Reported-by: Olof's autobuilder <build@lixom.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Earlier implementation assumed last instruction is BPF_EXIT.
Since this is no longer a restriction in eBPF, we remove this
limitation.
Per Alexei Starovoitov [1]:
> classic BPF has a restriction that last insn is always BPF_RET.
> eBPF doesn't have BPF_RET instruction and this restriction.
> It has BPF_EXIT insn which can appear anywhere in the program
> one or more times and it doesn't have to be last insn.
[1] https://lkml.org/lkml/2014/11/27/2
Fixes: e54bcde3d6 ("arm64: eBPF JIT compiler")
Acked-by: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
All functions declared in this file are gone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: re-order patches so modify board-dt-sam9]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
As AT91 !DT code is now removed, cleanup the PIT clocksource driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: split patch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
As putting data which is read mostly together, we can avoid
unnecessary cache line bouncing.
Other architectures, such as ARM and x86, adopted the same idea.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Jungseok Lee <jungseoklee85@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
vsys is the core always-on supply of the Marsboard.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
As at91rm9200 is now DT only, there is no need to keep old entry point in this
at91rm9200 System Timer (ST) driver.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: split patch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
GPIO and LED drivers were replaced by generic ones for DT boards. These drivers
were remaining: delete them now. Modifications are also done on the
corresponding header files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: split patch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The AT91-specific SoC strucutre "struct at91_init_soc" was filled with specific
!DT initilisation functions. Now that we got rid of the !DT board file
description, remove unneeded functions.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: split patch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
An explicit selection option is not needed for board files so now we select the
board from SoC option.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[nicolas.ferre@atmel.com: remove option's comments; split patch]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
IRQ support for Broadcom's bus-axi driver bcma was merged into John
Linville's wireless tree and will show up in 3.19. This patch makes use
of this feature in the DTS file for the the BCM5301X SoCs. I left the
PCIe controller out, because this still needs some discussion.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Update handling of cacheflush syscall with changes made in arch/arm
counterpart:
- return error to userspace when flushing syscall fails
- split user cache-flushing into interruptible chunks
- don't bother rounding to nearest vma
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
[will: changed internal return value from -EINTR to 0 to match arch/arm/]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Commit eb7e7d76 "s390: Replace __get_cpu_var uses" broke machine check
handling.
We copy machine check information from per-cpu to a stack variable for
local processing. Next we should zap the per-cpu variable, not the
stack variable.
Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Reviewed-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Acked-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
First, there was this: https://bugzilla.kernel.org/show_bug.cgi?id=88001
The problem there was that microcode patches are not being reapplied
after suspend-to-ram. It was important to reapply them, though, because
of for example Haswell's TSX erratum which disabled TSX instructions
with a microcode patch.
A simple fix was fb86b97300 ("x86, microcode: Update BSPs microcode
on resume") but, as it is often the case, simple fixes are too
simple. This one causes 32-bit resume to fail:
https://bugzilla.kernel.org/show_bug.cgi?id=88391
Properly fixing this would require more involved changes for which it
is too late now, right before the merge window. Thus, limit this to
64-bit only temporarily.
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1417353999-32236-1-git-send-email-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Add a DTS describing the Digilent ZYBO board. Similar to ZED but with
a 50MHz crystal instead of 33MHz.
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The fact that all supported boards use the same 33MHz crystal is a
co-incidence. The Zynq PS support a range of crystal freqs so the
hardcoded setting should be removed from the dtsi. Re-implement it
on the board level.
This prepares support for Zynq boards with different crystal
frequencies (e.g. the Digilent ZYBO).
Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current driver probe() function assumes the sensor device to be
always present and gets executed every time if the driver is loaded,
but the appropriate hardware could not be present.
So, move the platform device creation as part of platform init code
and use the 'id_table' to check if the device is present or not.
Signed-off-by: Neelesh Gupta <neelegup@linux.vnet.ibm.com>
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
The SDMMC, SDIO and EMMC controllers use an external FIFO whose size is 256x32bit.
This patch set the corresponding fifo-depth properties for both RK3066 and RK3188.
Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The leds-gpio driver recently switched to the device property API. The device_node
name is no longer retrieved if the "label" devicetree property is not found.
In this case the driver tries to create entries with (null) name in
/sys/class/leds, which is wrong and generates backtrace as several gpio_leds have
the same name. Also renamed subnode "yellow" to "blue" to match the last
schematics updates.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The suspend/resume sequence on Armada XP needs to modify a number of
registers in the SDRAM controller. Therefore, this commit updates the
Armada XP Device Tree description to include the SDRAM controller
Device Tree node.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-17-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to support suspend/resume on Armada XP, an additional set of
registers need to be described at the MBus controller level. This
commit therefore adjusts the Device Tree of the Armada 370/XP SoC to
include those registers in the MBus controller description;
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-16-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit improves the Armada XP GP Device Tree description to
describe the 3 GPIOs that are used to connect the SoC to the PIC
micro-controller that we talk to shutdown the SoC when entering
suspend to RAM.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-15-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada XP has multiple cores clocked by independent clocks. The
SMP startup code contains a function called set_secondary_cpus_clock()
called in armada_xp_smp_prepare_cpus() to ensure the clocks of the
secondary CPUs match the clock of the boot CPU.
With the introduction of suspend/resume, this operation is no longer
needed when booting the system, but also when existing the suspend to
RAM state. Therefore this commit reworks a bit the logic: instead of
configuring the clock of all secondary CPUs in
armada_xp_smp_prepare_cpus(), we do it on a per-secondary CPU basis in
armada_xp_boot_secondary(), as this function gets called when existing
suspend to RAM for each secondary CPU.
Since the function now only takes care of one CPU, we rename it from
set_secondary_cpus_clock() to set_secondary_cpu_clock(), and it looses
its __init marker, as it is now used beyond the system initialization.
Note that we can't use smp_processor_id() directly, because when
exiting from suspend to RAM, the code is apparently executed with
preemption enabled, so smp_processor_id() is not happy (prints a
warning). We therefore switch to using get_cpu()/put_cpu(), even
though we pretty much have the guarantee that the code starting the
secondary CPUs is going to run on the boot CPU and will not be
migrated.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-14-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The armada_370_xp_cpu_resume() until now was used only as the function
called by the SoC when returning from a deep idle state (as used in
cpuidle, or when the CPU is brought offline using CPU hotplug).
However, it is now also used when exiting the suspend to RAM state. In
this case, it is the bootloader that calls back into this function,
with the MMU left enabled by the BootROM. Having the MMU enabled when
entering this function confuses the kerrnel because we are not using
the kernel page tables at this point, but in other mvebu functions we
use the information on whether the MMU is enabled or not to find out
whether we should talk to the coherency fabric using a physical
address or a virtual address. To fix that, we simply disable the MMU
when entering this function, so that the kernel is in an expected
situation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-13-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On the Armada XP GP platform, entering suspend to RAM state is
triggering by talking to an external PIC micro-controller connected to
the SoC using 3 GPIOs. There is then a small magic sequence of GPIO
toggling that needs to be used to tell the PIC to turn off the SoC.
The code uses the Device Tree to find out which GPIOs are used to
connect to the PIC micro-controller, and then registers its
mvebu_armada_xp_gp_pm_enter() callback to the SoC-level PM code. The
SoC PM code will call back into this registered function at the very
end of the suspend procedure.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-12-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
When going out of suspend to RAM, the Marvell EBU platforms go through
the bootloader, which re-configures the DRAM controller. To achieve
this, the bootloader executes a piece of code called the "DDR3
training code". It does some reads/writes to the memory to find out
the optimal timings for the memory chip being used.
This has the nasty side effect that the first 10 KB of each DRAM
chip-select are overwritten by the bootloader when exiting the suspend
to RAM state.
Therefore, this commit implements the ->reserve() hook for the 'struct
machine_desc' used on Armada XP, to reserve the 10 KB of each DRAM
chip-select using the memblock API.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit implements the core of the platform code to enable
suspend/resume on Armada XP. It registers the platform_suspend_ops
structure, and implements the ->enter() hook of this structure.
It is worth mentioning that this commit only provides the SoC-level
part of suspend/resume, which calls into some board-specific code
provided in a follow-up commit.
The most important thing that this SoC-level code has to do is to
build an in-memory structure that contains a magic number, the return
address in the kernel after resume, and a set of address/value
pairs. This structure is used by the bootloader to restore a certain
number of registers (according to the set of address/value pairs) and
then jump back into the kernel at the provided location.
The code also puts the SDRAM into self-refresh mode, before calling
into board-specific code to actually enter the suspend to RAM state.
[ jac - add email exchange between Andrew Lunn and Thomas Petazzoni to better
describe who consumes the address/value pairs ]
> > Is this a well defined mechanism supported by mainline uboot, barebox
> > etc. Or is it some Marvell extension to their uboot?
>
> As far as I know, it is a Marvell extension to their "binary header",
> so it's done even before U-Boot starts. Since the hardware needs
> assistance from the bootloader to do suspend/resume, there is
> necessarily a certain amount of cooperation/agreement needed by what
> the kernel does and what the bootloader expects. I'm not sure there's
> any "standard" mechanism here. Do you know of any?
>
> I know the suspend/resume on the Blackfin architecture works the same
> way (at least it used to work that way years ago when I did a bit of
> Blackfin stuff). And here as well, there was some cooperation between
> the kernel and the bootloader. See
> arch/blackfin/mach-common/dpmc_modes.S, function do_hibernate() at the
> end.
>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
further clean up work.
Note that we still have dependencies to the legacy booting for
omap3 board-*.c files for setting up the board specific memory
timings. For that we need the timing related things still exposed
in include/linux/omap-gpmc.h. This will all become private data
to the GPMC driver once the legacy booting support can be dropped.
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Merge tag 'omap-for-v3.19/gpmc-move-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/omap-gpmc
Pull "move omap gpmc to drivers finally" from Tony Lindgren:
We can finally move the GPMC code to live in drivers/memory for
further clean up work.
Note that we still have dependencies to the legacy booting for
omap3 board-*.c files for setting up the board specific memory
timings. For that we need the timing related things still exposed
in include/linux/omap-gpmc.h. This will all become private data
to the GPMC driver once the legacy booting support can be dropped.
* tag 'omap-for-v3.19/gpmc-move-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
memory: gpmc: Move omap gpmc code to live under drivers
ARM: OMAP2+: Move GPMC initcall to devices.c
ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a single fix for a bug that was introduced back in v3.13.
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Merge tag 'tegra-for-3.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/fixes-non-critical
Pull "ARM: tegra: Core code changes for v3.19" from Thierry Reding:
This contains a single fix for a bug that was introduced back in v3.13.
* tag 'tegra-for-3.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Re-add removed SoC id macro to tegra_resume()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This is merely a regeneration of the default configuration to get rid of
two symbols that are now enabled by default or removed.
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Merge tag 'tegra-for-3.19-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/defconfig
Pull "ARM: tegra: Default configuration changes for v3.19" from Thierry Reding:
This is merely a regeneration of the default configuration to get rid of
two symbols that are now enabled by default or removed.
* tag 'tegra-for-3.19-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Regenerate default configuration
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The most important part is adding the axi bus to the SoC dtsi file,
this is the main bus on the SoC.
These patches were all send to the arm list and I haven't got any
negative responses.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Merge tag 'bcm5301x-dt-2014-11-27' of https://github.com/hauke/linux into next/dt
Pull "ARM: BCM5301X: Add some more devices to device tree" from Hauke Mehrtens:
The most important part is adding the axi bus to the SoC dtsi file,
this is the main bus on the SoC.
These patches were all send to the arm list and I haven't got any
negative responses.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* tag 'bcm5301x-dt-2014-11-27' of https://github.com/hauke/linux:
ARM: BCM5301X: Add LEDs for Netgear R6250 V1
ARM: BCM5301X: Add Broadcom's bus-axi to the DTS file
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
description" that generic timers provide an active-LOW interrupt
output. Fix the device trees to correctly describe this.
While doing this update the CPU mask to match the number of described
CPUs as well.
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just four simple fixes this week:
- one missing of_node_put() on armv7 based mvebu
- forcing the USB host into the right mode on Chromebook (exynos5-snow)
- enabling two important drivers for exynos_defconfig
- fixing a noncritical bug for tegra that would cause a
regression with common code patches queued for 3.19
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Merge tag 'armsoc-for-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Not much interesting going on fixes-wise for us this week, as it
should be for an -rc7. I'm not expecting Olof to work much over
Thanksgiving weekend, so I decided to take over again and push these
out to you.
Just four simple fixes this week:
- one missing of_node_put() on armv7 based mvebu
- forcing the USB host into the right mode on Chromebook
(exynos5-snow)
- enabling two important drivers for exynos_defconfig
- fixing a noncritical bug for tegra that would cause a regression
with common code patches queued for 3.19"
* tag 'armsoc-for-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: tegra: irq: fix buggy usage of irq_data irq field
ARM: exynos_defconfig: Enable max77802 rtc and clock drivers
ARM: dts: Explicitly set dr_mode on exynos5250-snow
ARM: mvebu: add missing of_node_put() call in coherency.c
Pull ARM fixes from Russell King:
"Another round of relatively small ARM fixes.
Thomas spotted that the strex backoff delay bit was a disable bit, so
it needed to be clear for this to work. Vladimir spotted that using a
restart block for the cache flush operation would return -EINTR, which
userspace was not expecting. Dmitry spotted that the auxiliary
control register accesses for Xscale were not correct"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8226/1: cacheflush: get rid of restarting block
ARM: 8222/1: mvebu: enable strex backoff delay
ARM: 8216/1: xscale: correct auxiliary register in suspend/resume
- mvebu
- Use simple-card audio on Armada 370 DB
- Add DSA node for Armada 370 DB
- Add SDHCI to Armada 38x
- Armada 370/XP rework to support new Synology boards
- Add Synology DS213j and DS414
- Various pinctrl and uart and alias fixes to help bootloaders
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Merge tag 'mvebu-dt-3.19-2' of git://git.infradead.org/linux-mvebu into next/dt
Pull "mvebu DT changes for v3.19 (round 2)" from Jason Cooper:
- mvebu
- Use simple-card audio on Armada 370 DB
- Add DSA node for Armada 370 DB
- Add SDHCI to Armada 38x
- Armada 370/XP rework to support new Synology boards
- Add Synology DS213j and DS414
- Various pinctrl and uart and alias fixes to help bootloaders
* tag 'mvebu-dt-3.19-2' of git://git.infradead.org/linux-mvebu:
arm: mvebu: normalize pinctrl entries for Armada SoCs
arm: mvebu: fix wrongly named DS414 pinctrl entries
arm: mvebu: add .dts file for Synology DS414
arm: mvebu: add .dts file for Synology DS213j
arm: mvebu: define and use common Armada XP SPI pinctrl setting
arm: mvebu: define and use common Armada XP UART2/3 pinctrl settings
arm: mvebu: define and use common Armada 370 UART pinctrl settings
arm: mvebu: define and use common Armada 370 SPI pinctrl settings
arm: mvebu: move Armada 370/XP pinctrl node definition armada-370-xp.dtsi
arm: mvebu: use recently introduced uart label for stdout-path
arm: mvebu: add uartX labels for Armada SoC serial nodes
arm: mvebu: fix vendor prefix typo in kirkwood-synology.dtsi
ARM: mvebu: fix ordering in Armada 370 .dtsi
ARM: mvebu: adjust ethernet aliases according to U-Boot requirements for A38x
ARM: mvebu: remove clock-frequency from Armada 38x SDHCI Device Tree node
ARM: mvebu: enable no-1-8-v flag for Armada 385 DB SDHCI interface
mvebu: 370 RD: Add support for the switch
ARM: mvebu: use simple-card DT binding for audio on Armada 370 DB
ARM: mvebu: remove conflicting muxing on Armada 370 DB
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Armada 38x
- Implement CPU hotplug support
- Armada 375
- Remove Z1 stepping support (limited dist. of SoC)
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Merge tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu into next/soc
Pull "mvebu SoC changes for v3.19" from Jason Cooper:
- Armada 38x
- Implement CPU hotplug support
- Armada 375
- Remove Z1 stepping support (limited dist. of SoC)
* tag 'mvebu-soc-3.19' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs
ARM: mvebu: Fix the secondary startup for Cortex A9 SoC
ARM: mvebu: Move SCU power up in a function
ARM: mvebu: Clean-up the Armada XP support
ARM: mvebu: update comments in coherency.c
ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency
ARM: mvebu: remove unused register offset definition
ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP
ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric
ARM: mvebu: Remove thermal quirk for A375 Z1 revision
ARM: mvebu: add missing of_node_put() call in coherency.c
ARM: orion: Fix for certain sequence of request_irq can cause irq storm
ARM: mvebu: armada xp: Generalize use of i2c quirk
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The MMCI driver, when used with a Device Tree described device, relies
on the "vmmc" voltage regulator supply to set the OCR register voltage bits,
using MMC core's mmc_regulator_get_supply() function.
Without the regulator framework present there are no valid operating
voltages reported and the device initialisation fails:
mmci-pl18x 10005000.mmci: No vmmc regulator found
mmci-pl18x 10005000.mmci: no support for card's volts
mmc0: error -22 whilst initialising SD card
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Just move to drivers as further clean-up can now happen there
finally.
Let's also add Roger and me to the MAINTAINERS so we get
notified for any patches related to GPMC.
Cc: Arnd Bergmann <arnd@arndb.de>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This will us allow to just move gpmc.c to live under drivers
in the next patch.
Note that we now also remove the omap specific check for the
initcall. That's OK as gpmc_probe() checks for the pdata
and bails out for other platforms compiled in.
Also the postcore_initcall() maybe possible to change to
just regular module_init(), but let's do that in separate
patch after the move to drivers is done.
Cc: Arnd Bergmann <arnd@arndb.de>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- removal of legacy board support for the last SoC having board C files: at91rm9200
- removal or modification of some Kconfig options
- switch to USE_OF for all the AT91 SoCs
- removal of the old AT91-specific clocks and IRQ drivers
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Merge tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup
Pull "Fourth batch of cleanup/SoC for 3.19" from Nicolas Ferre:
- removal of legacy board support for the last SoC having board C files: at91rm9200
- removal or modification of some Kconfig options
- switch to USE_OF for all the AT91 SoCs
- removal of the old AT91-specific clocks and IRQ drivers
* tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: remove unused IRQ function declarations
ARM: at91: remove legacy IRQ driver and related code
ARM: at91: remove old at91-specific clock driver
ARM: at91: remove clock data in at91sam9n12.c and at91sam9x5.c files
ARM: at91: remove all !DT related configuration options
ARM: at91/trivial: update Kconfig comment to mention SAMA5
ARM: at91: always USE_OF from now on
ARM: at91/Kconfig: remove ARCH_AT91RM9200 option for drivers
ARM: at91: switch configuration option to SOC_AT91RM9200
ARM: at91: remove at91rm9200 legacy board support
ARM: at91: remove at91rm9200 legacy boards files
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Initial revision of device tree for AMD Seattle Development platform.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: Thomas Lendacky <Thomas.Lendacky@amd.com>
Signed-off-by: Joel Schopp <Joel.Schopp@amd.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Now, with the CLCD DT support available, there is no
more reason to keep the non-DT support for V2P-CA9.
Removed, together with "some" supporting code. It was
necessary to make PLAT_VERSATILE_SCHED_CLOCK optional
and selected by the machines still interested in it.
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since there is no public documentation, this patch also provide register
offsets for different UART units on this SoC.
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This enables the simple framebuffer on all the supported Allwinner SoCs (but
the A80). That allows to have at last a video display usable by using the
framebuffer the firmware might have set up.
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Merge tag 'sunxi-simplefb-for-3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt
Pull "Allwinner simple frambuffer support" from Maxime Ripard:
This enables the simple framebuffer on all the supported Allwinner SoCs (but
the A80). That allows to have at last a video display usable by using the
framebuffer the firmware might have set up.
* tag 'sunxi-simplefb-for-3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (55 commits)
ARM: dts: sunxi: Update simplefb nodes so that u-boot can find them
ARM: dts: sunxi: Add de_be0 clk parent pll to simplefb node
ARM: dts: sun7i: Add simplefb node
ARM: dts: sun6i: Add simplefb node
ARM: dts: sun5i: Add simplefb node
ARM: dts: sun4i: Add simplefb node
ARM: dts: sun6i: Add ethernet support to M9 board
ARM: sun6i: DT: Add PLL6 multiple outputs
ARM: dts: sun6i: Add support for the status led
ARM: dts: sun6i: Add EHCI support for the M9 board
ARM: dts: sunxi: Add regulator-boot-on property to ahci-5v regulator
ARM: dts: sun7i: Cubietruck: add power supply regulator for USB OTG VBUS
ARM: dts: sun7i: Cubietruck: override regulator pin
ARM: sun7i: dtsi: add support for usbphy0
ARM: dtsi: sunxi: add common VBUS regulator
ARM: dts: sunxi: Banana Pi: increase startup-delay for the GMAC PHY regulator
ARM: sun5i: olinuxino: Relicense the device tree under GPLv2/X11
ARM: sun4i: cubieboard: Relicense the device tree under GPLv2/X11
ARM: sun7i: pcduino3: Relicense the device tree under GPLv2/X11
ARM: sun4i: pcduino: Relicense the device tree under GPLv2/X11
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Device additions for board vf610-colibri, pwm, backlight, I2C, RTC,
ADC etc.
- Update i.MX6 phyFLEX board to include PCIe, CAN and audio support
- Improve SSI clocks description for i.MX5 platforms
- Add ENET2 support for imx6sx-sdb board
- Add device tree source for LS1021A SoC, board QDS and TWR
- Enable cpufreq support for i.MX53
- Enable VPU device support for i.MX6QDL
- Enable poweroff support for i.MX6 SoCs
- Add support for TBS2910 Matrix ARM mini PC which is built on i.MX6Q
- Create generic base device trees for Vybrid and add support for
Colibri VF50
Note: the change set is built on top of imx-soc-3.19 to resolve the
dependency that "ARM: dts: imx53: add cpufreq-dt support" uses the
clock define IMX5_CLK_ARM that is added by "ARM: imx53: clk: add ARM
clock".
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Merge tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Pull "The i.MX device tree changes for 3.19" from Shawn Guo:
- Device additions for board vf610-colibri, pwm, backlight, I2C, RTC,
ADC etc.
- Update i.MX6 phyFLEX board to include PCIe, CAN and audio support
- Improve SSI clocks description for i.MX5 platforms
- Add ENET2 support for imx6sx-sdb board
- Add device tree source for LS1021A SoC, board QDS and TWR
- Enable cpufreq support for i.MX53
- Enable VPU device support for i.MX6QDL
- Enable poweroff support for i.MX6 SoCs
- Add support for TBS2910 Matrix ARM mini PC which is built on i.MX6Q
- Create generic base device trees for Vybrid and add support for
Colibri VF50
Note: the change set is built on top of imx-soc-3.19 to resolve the
dependency that "ARM: dts: imx53: add cpufreq-dt support" uses the
clock define IMX5_CLK_ARM that is added by "ARM: imx53: clk: add ARM
clock".
* tag 'imx-dt-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (51 commits)
ARM: dts: imx6q-tbs2910: Enable snvs-poweroff
ARM: dts: imx6: add pm_power_off support for i.mx6 chips
ARM: dts: vf-colibri: add USB regulators
ARM: dts: imx6: phyFLEX: Add CAN support
ARM: dts: imx6: phyFLEX: Add PCIe
ARM: dts: imx6: phyFLEX: Set correct interrupt for pmic
ARM: dts: imx6: phyFLEX: Enable gpmi in module file
ARM: dts: imx6: phyFLEX: set nodes in alphabetical order
ARM: dts: vf-colibri-eval-v3.dts: Enable ST-M41T0M6 RTC
ARM: dts: vf-colibri: Add I2C support
ARM: dts: imx6qdl: Enable CODA960 VPU
ARM: dts: imx6q-tbs2910: Remove unneeded 'fsl,mode' property
ARM: dts: vf610: enable USB misc/phy nodes where necessary
ARM: dts: vf610: use new GPIO support
ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boards
ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02
ARM: dts: vf500-colibri: add Colibri VF50 support
ARM: dts: vf610: create generic base device trees
ARM: dts: vf610: assign oscillator to clock module
dt-bindings: arm: add Freescale LS1021A SoC device tree binding
...
Signed-off-by; Arnd Bergmann <arnd@arndb.de>
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
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Merge tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Pull "The i.MX SoC update for 3.19" from Shawn Guo
- Update i.MX6 suspend code to check DDR instead of CPU type, as the
difference we need to handle is between LPDDR2 and DDR3, not SoCs.
- Set anatop properly for LPDDR2 in DSM mode
- Add support for new SoC LS1021A which integrates dual Cortex-A7
- Add ENET initialization for i.MX6SX platform
- Add cpufreq support for i.MX53 platform
- Add a SNVS based poweroff driver for i.MX6 platforms
- Use ARM Global Timer as clocksource on VF610
Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
* tag 'imx-soc-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
ARM: imx: clk-vf610: get input clocks from assigned clocks
ARM: imx: Add Freescale LS1021A SMP support
ARM: imx: Add initial support for Freescale LS1021A
ARM: imx53: add cpufreq support
ARM: imx53: clk: add ARM clock
ARM: imx: add CPU clock type
ARM: imx5: add step clock, used when reprogramming PLL1
ARM: imx: add enet init for i.mx6sx
ARM: imx6sx: add imx6sx iomux-gpr field define
ARM: vf610: Add ARM Global Timer clocksource option
ARM: imx: add anatop settings for LPDDR2 when enter DSM mode
ARM: imx: replace cpu type check with ddr type check
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
Signed-off-by; Arnd Bergmann <arnd@arndb.de>
- Clean up reset handler for DT machines, since reset has been handled
in watchdog driver
- Remove unneeded .map_io hook for a couple of i.MX6 machines
- A few small i.MX6 device tree source cleanups
- Some random iomuxc and pllv3 code cleanup
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Merge tag 'imx-cleanup-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/cleanup
Pull "The i.MX cleanup for 3.19" from Shawn Guo:
- Clean up reset handler for DT machines, since reset has been handled
in watchdog driver
- Remove unneeded .map_io hook for a couple of i.MX6 machines
- A few small i.MX6 device tree source cleanups
- Some random iomuxc and pllv3 code cleanup
* tag 'imx-cleanup-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Remove unneeded .map_io initialization
ARM: dts: imx6qdl-sabresd: Fix the microphone route
ARM: imx: refactor mxc_iomux_mode()
ARM: imx: simplify clk_pllv3_prepare()
ARM: imx6q: drop unnecessary semicolon
ARM: imx: clean up machine mxc_arch_reset_init_dt reset init
ARM: dts: imx6qdl-rex: Remove unneeded 'fsl,mode' property
ARM: dts: imx6qdl-gw5x: Remove unneeded 'fsl,mode' property
ARM: dts: imx6qdl-sabresd: Use IMX6QDL_CLK_CKO define
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SoC related changes for omaps including hwmod clean-up for
DSS, and hwmod data for more UARTs and ADC. Also few defconfig
changes to enable devices found on am335x and am437x.
[arnd: I removed the defconfig changes from the branch in order
to cherry-pick them onto the next/defconfig branch, but I did
not change the other commits]
* commit '29c4ce17bcad':
ARM: dts: cm-t3x30: add keypad support
ARM: OMAP2+: hwmod: AM43x: add hwmod support for ADC on AM43xx
ARM: DRA7: hwmod data: Add missing UART hwmod data
ARM: dts: omap4.dtsi: remove dss_fck
ARM: OMAP4: fix RFBI iclk
ARM: OMAP4: hwmod: use MODULEMODE properly
ARM: OMAP4: hwmod: set DSS submodule parent hwmods
ARM: OMAP5: hwmod: set DSS submodule parent hwmods
ARM: OMAP2+: hwmod: add parent_hwmod support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- exynos3250
: add PMU support
- PMU refactoring
: move restart code into PMU driver
: move restart code for exynos440 into clk driver
- use u8 for val[] in struct exynos_pmu_conf
Note that this branch is based on tags/samsung-exynos-v3.19
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Merge tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim:
- exynos3250
: add PMU support
- PMU refactoring
: move restart code into PMU driver
: move restart code for exynos440 into clk driver
- use u8 for val[] in struct exynos_pmu_conf
Note that this branch is based on tags/samsung-exynos-v3.19
* tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
ARM: EXYNOS: move restart code into pmu driver
clk: exynos5440: move restart code into clock driver
ARM: EXYNOS: add exynos3250 PMU support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- add SOC_EXYNOS4415 config to be used in audio driver
- add support platform driver for exynos PMU
- move PMU specific definitions from common.h to exynos-pmu.h
- for exynos5420, add support PMU and Suspend-to-RAM
use MCPM call backs and call regulator core suspend prepare
and finish functions
NOTE:
including v3.19-next/non-critical-fixes, v3.19-next/cleanup-samsung
and v3.19-next/pm-samsung-2 branches
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Merge tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Pull "Samsung exynos updates in arch/arm/mach-exynos/ for v3.19" from Kukjin Kim:
- add SOC_EXYNOS4415 config to be used in audio driver
- add support platform driver for exynos PMU
- move PMU specific definitions from common.h to exynos-pmu.h
- for exynos5420, add support PMU and Suspend-to-RAM
use MCPM call backs and call regulator core suspend prepare
and finish functions
NOTE:
including v3.19-next/non-critical-fixes, v3.19-next/cleanup-samsung
and v3.19-next/pm-samsung-2 branches
* tag 'samsung-exynos-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Call regulator core suspend prepare and finish functions
ARM: EXYNOS: Use MCPM call-backs to support S2R on exynos5420
ARM: EXYNOS: Add Suspend-to-RAM support for exynos5420
ARM: EXYNOS: Add PMU support for exynos5420
ARM: EXYNOS: Move PMU specific definitions from common.h
ARM: EXYNOS: Add platform driver support for Exynos PMU
ARM: EXYNOS: Add support for exynos4415 SoC
ARM: EXYNOS: fix typo in static struct name "exynos5_list_diable_wfi_wfe"
ARM: EXYNOS: Fix CPU idle clock down after CPU off
ARM: EXYNOS: Remove unneeded __ref annotation for cpu_die function
ARM: EXYNOS: Move code from hotplug.c to platsmp.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- fix typo in static struct name "exynos5_list_diable_wfi_wfe"
: it should be "exynos5_list_disable_wfi_wfe"
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Merge tag 'samsung-fixes-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/fixes-non-critical
Pull "Samsung non-critical-fixes for v3.19" from Kukjin Kim:
- fix typo in static struct name "exynos5_list_diable_wfi_wfe"
: it should be "exynos5_list_disable_wfi_wfe"
* tag 'samsung-fixes-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: fix typo in static struct name "exynos5_list_diable_wfi_wfe"
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
run again, until the patches for using the physical architected
timers got accepted.
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Merge tag 'v3.19-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "temporarily disable rk3288-smp" from Heiko Stuebner:
Disable smp again on rk3288 temporarily to make Olof's boottest
run again, until the patches for using the physical architected
timers got accepted.
* tag 'v3.19-rockchip-dts3' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: temporarily disable smp on rk3288
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The dma_mask and coherent_dma_mask need to be set or DMA memory allocations
will fail with error messages like this:
ep93xx-dma ep93xx-dma-m2p: coherent DMA mask is unset
ep93xx-dma ep93xx-dma-m2m: coherent DMA mask is unset
Add the missing information to the ep93xx-dma-m2p and ep93xx-dma-m2m
devices.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reported-by: Jeremy Moles <cubicool@gmail.com>
Tested-by: Alexander Sverdlin <subaparts@yandex.ru>
Cc: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
secure_computing() is called first in syscall_trace_enter() so that
a system call will be aborted quickly without doing succeeding syscall
tracing if seccomp rules want to deny that system call.
On compat task, syscall numbers for system calls allowed in seccomp mode 1
are different from those on normal tasks, and so _NR_seccomp_xxx_32's need
to be redefined.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
SIGSYS is primarily used in secure computing to notify tracer of syscall
events. This patch allows signal handler on compat task to get correct
information with SA_SIGINFO specified when this signal is delivered.
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
If tracer modifies a syscall number to -1, this traced system call should
be skipped with a return value specified in x0.
This patch implements this semantics.
Please note:
* syscall entry tracing and syscall exit tracing (ftrace tracepoint and
audit) are always executed, if enabled, even when skipping a system call
(that is, -1).
In this way, we can avoid a potential bug where audit_syscall_entry()
might be called without audit_syscall_exit() at the previous system call
being called, that would cause OOPs in audit_syscall_entry().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[will: fixed up conflict with blr rework]
Signed-off-by: Will Deacon <will.deacon@arm.com>
This regeset is intended to be used to get and set a system call number
while tracing.
There was some discussion about possible approaches to do so:
(1) modify x8 register with ptrace(PTRACE_SETREGSET) indirectly,
and update regs->syscallno later on in syscall_trace_enter(), or
(2) define a dedicated regset for this purpose as on s390, or
(3) support ptrace(PTRACE_SET_SYSCALL) as on arch/arm
Thinking of the fact that user_pt_regs doesn't expose 'syscallno' to
tracer as well as that secure_computing() expects a changed syscall number,
especially case of -1, to be visible before this function returns in
syscall_trace_enter(), (1) doesn't work well.
We will take (2) since it looks much cleaner.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Pull mips fixes from Ralf Baechle:
"The hopefully final round of fixes for 3.18:
- Fix a number of build errors affecting particular configurations.
- Handle EVA correctly when flushing a signal trampoline and dcache
lines.
- Fix printks printing jibberish.
- Handle 64 bit memory addresses correctly when adding memory chunk
on 32 bit kernels.
- Fix a race condition in the hardware tablewalker code"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers
MIPS: Fix address type used for early memory detection.
MIPS: Kconfig: Don't allow both microMIPS and SmartMIPS to be selected.
MIPS: kernel: cps-vec: Set ISA level to mips32r2 for the MIPS MT ASE
MIPS: Netlogic: handle modular AHCI builds
MIPS: Netlogic: handle modular USB case
MIPS: Loongson: Make platform serial setup always built-in.
MIPS: fix EVA & non-SMP non-FPU FP context signal handling
MIPS: cpu-probe: Set the FTLB probability bit on supported cores
MIPS: BMIPS: Fix ".previous without corresponding .section" warnings
MIPS: uaccess.h: Fix strnlen_user comment.
MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line
MIPS: Fix info about plat_setup in arch_mem_init comment
MIPS: rtlx: Remove KERN_DEBUG from pr_debug() arguments in rtlx.c
MIPS: SEAD3: Fix LED device registration.
MIPS: Fix a copy & paste error in unistd.h
Pull powerpc fixes from Michael Ellerman:
"Here are five fixes for you to pull please.
They're all CC'ed to stable except the "Fix PE state format" one which
went in this release"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux:
powerpc: 32 bit getcpu VDSO function uses 64 bit instructions
powerpc/powernv: Replace OPAL_DEASSERT_RESET with EEH_RESET_DEACTIVATE
powerpc/eeh: Fix PE state format
powerpc/pseries: Fix endiannes issue in RTAS call from xmon
powerpc/powernv: Fix the hmi event version check.
Pull sparc fixlet from David Miller:
"Aparc fix to add dma_cache_sync(), even if a nop it should be provided
if dma_{alloc,free}_noncoherent() is provided too"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
sparc: Add NOP dma_cache_sync() implementation.
This has been successfully tested on Netgear R6250 and two other
development (unnamed) devices, all of them BCM4708 based.
We also got a possitive feedback from R7000 (BCM4709) tester.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
There is a potential race when probing the TLB in TLBL/M/S exception
handlers for a matching entry. Between the time we hit a TLBL/S/M
exception and the time we get to execute the TLBP instruction, the
HTW may have replaced the TLB entry we are interested in hence the TLB
probe may fail. However, in the existing handlers, we never checked the
status of the TLBP (ie check the result in the C0/Index register). We
fix this by adding such a check when the core implements the HTW. If
we couldn't find a matching entry, we return back and try again.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We cannot restart cacheflush safely if a process provides user-defined
signal handler and signal is pending. In this case -EINTR is returned
and it is expected that process re-invokes syscall. However, there are
a few problems with that:
* looks like nobody bothers checking return value from cacheflush
* but if it did, we don't provide the restart address for that, so the
process has to use the same range again
* ...and again, what might lead to looping forever
So, remove cacheflush restarting code and terminate cache flushing
as early as fatal signal is pending.
Cc: stable@vger.kernel.org # 3.12+
Reported-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Under extremely rare conditions, in an MPCore node consisting of at
least 3 CPUs, two CPUs trying to perform a STREX to data on the same
shared cache line can enter a livelock situation.
This patch enables the HW mechanism that overcomes the bug. This fixes
the incorrect setup of the STREX backoff delay bit due to a wrong
description in the specification.
Note that enabling the STREX backoff delay mechanism is done by
leaving the bit *cleared*, while the bit was currently being set by
the proc-v7.S code.
[Thomas: adapt to latest mainline, slightly reword the commit log, add
stable markers.]
Fixes: de4901933f ("arm: mm: Add support for PJ4B cpu and init routines")
Cc: <stable@vger.kernel.org> # v3.8+
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since 3b26f39b0a (ARM: at91: make use of the new AIC driver for dt enabled
boards) the old IRQ initialisation functions aren't used anymore: remove their
declaration in generic.h.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Remove irc.c and associated header file. The related code was idendified by
the CONFIG_OLD_IRQ_AT91 option that was removed previously. It has been spotted
by following coccinelle semantic match:
@rule1@
expression E;
statement S;
@@
(
- if (IS_ENABLED(CONFIG_OLD_IRQ_AT91)) S
|
- if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && E) S
)
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
- enable max77802 rtc and clock drivers for exynos_defconfig
: enable the kernel config options to have the drivers for
max77802 including rtc and 2-ch 32kHz clock outputs
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Merge tag 'samsung-defconfig-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Pull "Samsung defconfig update for v3.18" from Kukjin Kim:
- enable max77802 rtc and clock drivers for exynos_defconfig
: enable the kernel config options to have the drivers for
max77802 including rtc and 2-ch 32kHz clock outputs
* tag 'samsung-defconfig-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: exynos_defconfig: Enable max77802 rtc and clock drivers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- explicitly set dr_mode on exynos5250-snow
this is required when kernel is built with USB gadget support.
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Merge tag 'samsung-fixes-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Pull "Samsung fixes for v3.18" from Kukjin Kim:
- explicitly set dr_mode on exynos5250-snow
this is required when kernel is built with USB gadget support.
* tag 'samsung-fixes-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Explicitly set dr_mode on exynos5250-snow
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The crazy gic_arch_extn thing that Tegra uses contains multiple
references to the irq field in struct irq_data, and uses this
to directly poke hardware register.
But irq is the *virtual* irq number, something that has nothing
to do with the actual HW irq (stored in the hwirq field). And once
we put the stacked domain code in action, the whole thing explodes,
as these two values are *very* different:
root@bacon-fat:~# cat /proc/interrupts
CPU0 CPU1
16: 25801 2075 GIC 29 twd
17: 0 0 GIC 73 timer0
112: 0 0 GPIO 58 c8000600.sdhci cd
123: 0 0 GPIO 69 c8000200.sdhci cd
279: 1126 0 GIC 122 serial
281: 0 0 GIC 70 7000c000.i2c
282: 0 0 GIC 116 7000c400.i2c
283: 0 0 GIC 124 7000c500.i2c
284: 300 0 GIC 85 7000d000.i2c
[...]
Just replacing all instances of irq with hwirq fixes the issue.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
I used some 64 bit instructions when adding the 32 bit getcpu VDSO
function. Fix it.
Fixes: 18ad51dd34 ("powerpc: Add VDSO version of getcpu")
Cc: stable@vger.kernel.org
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The flag passed to ioda_eeh_phb_reset() should be EEH_RESET_DEACTIVATE,
which is translated to OPAL_DEASSERT_RESET or something else by the
EEH backend accordingly.
The patch replaces OPAL_DEASSERT_RESET with EEH_RESET_DEACTIVATE for
ioda_eeh_phb_reset().
Cc: stable@vger.kernel.org
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Obviously I had wrong format given to the PE state output from
/sys/bus/pci/devices/xxxx/eeh_pe_state with some typoes, which
was introduced by commit 2013add4ce. The patch fixes it up.
Fixes: 2013add4ce ("powerpc/eeh: Show hex prefix for PE state sysfs")
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
On pseries system (LPAR) xmon failed to enter when running in LE mode,
system is hunging. Inititating xmon will lead to such an output on the
console:
SysRq : Entering xmon
cpu 0x15: Vector: 0 at [c0000003f39ffb10]
pc: c00000000007ed7c: sysrq_handle_xmon+0x5c/0x70
lr: c00000000007ed7c: sysrq_handle_xmon+0x5c/0x70
sp: c0000003f39ffc70
msr: 8000000000009033
current = 0xc0000003fafa7180
paca = 0xc000000007d75e80 softe: 0 irq_happened: 0x01
pid = 14617, comm = bash
Bad kernel stack pointer fafb4b0 at eca7cc4
cpu 0x15: Vector: 300 (Data Access) at [c000000007f07d40]
pc: 000000000eca7cc4
lr: 000000000eca7c44
sp: fafb4b0
msr: 8000000000001000
dar: 10000000
dsisr: 42000000
current = 0xc0000003fafa7180
paca = 0xc000000007d75e80 softe: 0 irq_happened: 0x01
pid = 14617, comm = bash
cpu 0x15: Exception 300 (Data Access) in xmon, returning to main loop
xmon: WARNING: bad recursive fault on cpu 0x15
The root cause is that xmon is calling RTAS to turn off the surveillance
when entering xmon, and RTAS is requiring big endian parameters.
This patch is byte swapping the RTAS arguments when running in LE mode.
Cc: stable@vger.kernel.org
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
The current HMI event structure is an ABI and carries a version field to
accommodate future changes without affecting/rearranging current structure
members that are valid for previous versions.
The current version check "if (hmi_evt->version != OpalHMIEvt_V1)"
doesn't accomodate the fact that the version number may change in
future.
If firmware starts returning an HMI event with version > 1, this check
will fail and no HMI information will be printed on older kernels.
This patch fixes this issue.
Cc: stable@vger.kernel.org # 3.17+
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
[mpe: Reword changelog]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This patch adds syscon based phandle to i2c device nodes of exynos5250
and exynos5420. These phandles will be used to save restore i2c sysreg
configuration register during s2r from i2c driver.
CC: Rob Herring <robh+dt@kernel.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Russell King <linux@arm.linux.org.uk>
CC: devicetree@vger.kernel.org
CC: linux-doc@vger.kernel.org
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Values stored in val[] are never bigger than a byte.
text data bss dec hex filename
7716 3692 8 11416 2c98 arch/arm/mach-exynos/pmu.o.before
5436 1908 8 7352 1cb8 arch/arm/mach-exynos/pmu.o.after
Cc: Pankaj Dubey <pankaj.dubey@samsung.com>
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This clock driver collection was specific to AT91 and only used in !DT cases.
All clocks and the clock trees for all Atmel SoCs are now described by drivers
using the common clock framework.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
As the CONFIG_OLD_CLK_AT91 option is gone, let's completely remove the AT91
old clock driver related data.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
This patch removes unused dt node of command line from Exynos3250-based
Rinato board because kernel use the command line from bootloader.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds new board dts file to support Samsung Monk board which
is based on Exynos3250 SoC and has different H/W configuration from
Rinato.
This dts file support following features:
- eMMC
- Main PMIC (Samsung S2MPS14)
- Interface PMIC (Maxim MAX77836, MUIC, fuel-gauge, charger)
- RTC of Exynos3250
- ADC of Exynos3250 with NTC thermistor
- I2S of Exynos3250
- TMU of Exynos3250
- Secure firmware for Exynos3250 secondary cpu boot
- Serial ports of Exynos3250
- gpio-key for power key
Signed-off-by: Youngjun Cho <yj44.cho@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The head.text section is intended to be run at early bootup
before any of the regular kernel mappings have been setup.
Parts of head.text may be freed back into the buddy allocator
due to TEXT_OFFSET so for security requirements this memory
must not be executable. The suspend/resume/hotplug code path
requires some of these head.S functions to run however which
means they need to be executable. Support these conflicting
requirements by moving the few head.text functions that need
to be executable to the text section which has the appropriate
page table permissions.
Tested-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In the arm64 arch_static_branch implementation we place an A64 NOP into
the instruction stream and log relevant details to a jump_entry in a
__jump_table section. Later this may be replaced with an immediate
branch without link to the code for the unlikely case.
At init time, the core calls arch_jump_label_transform_static to
initialise the NOPs. On x86 this involves inserting the optimal NOP for
a given microarchitecture, but on arm64 we only use the architectural
NOP, and hence replace each NOP with the exact same NOP. This is
somewhat pointless.
Additionally, at module load time we don't call jump_label_apply_nops to
patch the optimal NOPs in, unlike other architectures, but get away with
this because we only use the architectural NOP anyway. A later notifier
will patch NOPs with branches as required.
Similarly to x86 commit 11570da1c5 (x86/jump-label: Do not bother
updating NOPs if they are correct), we can avoid patching NOPs with
identical NOPs. Given that we only use a single NOP encoding, this means
we can NOP-out the body of arch_jump_label_transform_static entirely. As
the default __weak arch_jump_label_transform_static implementation
performs a patch, we must use an empty function to achieve this.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jiang Liu <liuj97@gmail.com>
Cc: Laura Abbott <lauraa@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In a similar manner to arm, it's useful to be able to dump the page
tables to verify permissions and memory types. Add a debugfs file
to check the page tables.
Acked-by: Steve Capper <steve.capper@linaro.org>
Tested-by: Steve Capper <steve.capper@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
[will: s/BUFFERABLE/NORMAL-NC/]
Signed-off-by: Will Deacon <will.deacon@arm.com>
OLD_CLK_AT91 & OLD_IRQ_AT91 were only selected by entries in Kconfig.non_dt
that are now gone. So we remove all this legacy stuff and select the proper
options in the SOC_ entries.
As USE_OF is now selected directly in arch/arm/Kconfig AT91 entry, we can
safely remove it everywhere in this file.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cortex-A5 SAMA5 processors were not listed, add this in the AT91 comment.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
As we always use Device Tree now, we can add the configuration here.
Also remove the condition for PINCTRL_AT91.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
This reverts commit 85c8555ff0 ("KVM: check for !is_zero_pfn() in
kvm_is_mmio_pfn()") and renames the function to kvm_is_reserved_pfn.
The problem being addressed by the patch above was that some ARM code
based the memory mapping attributes of a pfn on the return value of
kvm_is_mmio_pfn(), whose name indeed suggests that such pfns should
be mapped as device memory.
However, kvm_is_mmio_pfn() doesn't do quite what it says on the tin,
and the existing non-ARM users were already using it in a way which
suggests that its name should probably have been 'kvm_is_reserved_pfn'
from the beginning, e.g., whether or not to call get_page/put_page on
it etc. This means that returning false for the zero page is a mistake
and the patch above should be reverted.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Instead of using kvm_is_mmio_pfn() to decide whether a host region
should be stage 2 mapped with device attributes, add a new static
function kvm_is_device_pfn() that disregards RAM pages with the
reserved bit set, as those should usually not be mapped as device
memory.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
When running on a system with a GICv3, we currenly don't allow the guest
to access the system register interface of the GICv3. We do this by
clearing the ICC_SRE_EL2.Enable, which causes all guest accesses to
ICC_SRE_EL1 to trap to EL2 and causes all guest accesses to other ICC_
registers to cause an undefined exception in the guest.
However, we currently don't handle the trap of guest accesses to
ICC_SRE_EL1 and will spill out a warning. The trap just needs to handle
the access as RAZ/WI, and a guest that tries to prod this register and
set ICC_SRE_EL1.SRE=1, must read back the value (which Linux already
does) to see if it succeeded, and will thus observe that ICC_SRE_EL1.SRE
was not set.
Add the simple trap handler in the sorted table of the system registers.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
[ardb: added cp15 handling]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
omap_hsmmc only supports one slot. So slot id is always zero, and
slot id was never used in the callbacks anyway
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
omap_hsmmc supports only one slot per controller, see OMAP_MMC_MAX_SLOTS.
This unnecessary indirection leads to confusion in the omap_hsmmc driver.
For example the card_detect callback is not installed by platform code
but from the driver probe function. So it should be a field of
omap_hsmmc_host. But since it is declared under the platform slot while
the drivers struct omap_hsmmc_host has no slot abstraction, this looks
like a bug, especially when not familiar that this driver only supports
1 slot anyway.
Either we should add a slot abstraction to omap_hsmmc_host or remove
it from the platform data struct. Removed since slot multiplexing is
an un-implemented feature
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
trigger of this callback has been removed in 0a82e06e61
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
these fields are never read, probably an unimplemented feature
or superseded by pm_runtime
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
platform data is built from omap2_hsmmc_info, remove all fields that
are never set in omap_hsmmc_info, hence never copied to platform data.
Note that the omap_hsmmc driver is not affected by this patch those
fields were completely unused.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
- omap mmc driver supports multiplexing, omap_mmc_hs doesn't
this leads to one of the major confusions in the omap_hsmmc driver
- platform data should be read-only for the driver
most callbacks are not set by the omap3 platform init code while still
required. So they are set from the driver probe function, which is against
the paradigm that platform-data should not be modified by the driver
typical examples are card_detect, read_only callbacks
un-bundling by searching for driver name \"omap_hsmmc in the
arch/arm folder. omap_hsmmc_platform_data is not initialized directly,
but from omap2_hsmmc_info, which is defined in a separate header file
not touched by this patch
hwmod includes platform headers to declare features of the platform. All
the declared features are prefixed OMAP_HSMMC. There is no need to
include platform header from hwmod other except for feature defines
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Only a few files really need that platform header. When later splitting
omap_mmc_platform_data into omap_mmc and omap_mmc_hs, those files
declaring an hs mmc platform data will have to change the platform
include, which is a good sanity check.
Also removing omap242x_init_mmc, which is not used anywhere, checked
with grep.
Signed-off-by: Andreas Fenkart <afenkart@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Every other architecture with permanent fixed addresses has
FIX_HOLE as the first entry. This seems to be designed as a
debugging aid but there are a couple of side effects of not
having FIX_HOLE:
- If the first fixed address is 0, fix_to_virt -> virt_to_fix
triggers a BUG_ON for the virtual address being equal to
FIXADDR_TOP
- fix_to_virt may return a value outside of FIXADDR_START
and FIXADDR_TOP which may look like a bug to a developer.
Match up with other architectures and make everything clearer
by adding FIX_HOLE.
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and
64-bit ARM architectures, move the common definition to drivers/amba
where dependent drivers will be located.
Signed-off-by: Thierry Reding <treding@nvidia.com>
There are currently 2 differents naming conventions used between the
existing Armada SoC DT files for pinctrl entries (*_pin(s): *-pin(s)
and pmx_*: pmx-*) with a vast majority of files using the former:
$ grep _pin arch/arm/boot/dts/armada-*.dts* | wc -l
155
$ grep pmx arch/arm/boot/dts/armada-*.dts* | wc -l
13
In fact, only some Armada XP files are using the second variant.
This patch normalizes those files (mainly ge0/1 entries) to use
the first variant.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/00114c3169e1d93259ff4150ed46ee36eae16b1e.1416670812.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
While renaming pinctrl entries during reviews of Synology DS414 support
series, I missed three entries, as reported by Ben. This patch fixes
those.
Reported-by: Ben Peddell <klightspeed@killerwolves.net>
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Link: https://lkml.kernel.org/r/608e4fd6e06e9c5289a84b9c38e81b2456dbcd79.1416670812.git.arno@natisbad.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The commit "genirq: Generic chip: Change irq_reg_{readl,writel}
arguments" modified the API. In the same tome the
arch/arm/plat-orion/gpio.c file received a fix with the use of the old
API: "ARM: orion: Fix for certain sequence of request_irq can cause
irq storm". This commit fixes the use of the API.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Olof Johansson <olof@lixom.net>
Link: https://lkml.kernel.org/r/1416928752-24529-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
.exit.* sections may be subject to patching by the new alternatives
framework and so shouldn't be discarded at link-time. Without this patch,
such a section will result in the following linker error:
`.exit.text' referenced in section `.altinstructions' of
drivers/built-in.o: defined in discarded section `.exit.text' of
drivers/built-in.o
Signed-off-by: Will Deacon <will.deacon@arm.com>
The fixmap API was originally added for arm64 for
early_ioremap purposes. It can be used for other purposes too
so move the initialization from ioremap to somewhere more
generic. This makes it obvious where the fixmap is being set
up and allows for a cleaner implementation of __set_fixmap.
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The function cpu_resume currently lives in the .data section.
There's no reason for it to be there since we can use relative
instructions without a problem. Move a few cpu_resume data
structures out of the assembly file so the .data annotation
can be dropped completely and cpu_resume ends up in the read
only text section.
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Kees Cook <keescook@chromium.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The hyp stub vectors are currently loaded using adr. This
instruction has a +/- 1MB range for the loading address. If
the alignment for sections is changed the address may be more
than 1MB away, resulting in reclocation errors. Switch to using
adrp for getting the address to ensure we aren't affected by the
location of the __hyp_stub_vectors.
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
handle_arch_irq isn't actually text, it's just a function pointer.
It doesn't need to be stored in the text section and doing so
causes problesm if we ever want to make the kernel text read only.
Declare handle_arch_irq as a proper function pointer stored in
the data section.
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
While we currently expect self-hosted debug support to be identical
across CPUs, we don't currently sanity check this.
This patch adds logging of the ID_AA64DFR{0,1}_EL1 values and associated
sanity checking code.
It's not clear to me whether we need to check PMUVer, TraceVer, and
DebugVer, as we don't currently rely on these fields at all.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
A missing newline in the WARN_TAINT_ONCE string results in ugly and
somewhat difficult to read output in the case of a sanity check failure,
as the next print does not appear on a new line:
Unsupported CPU feature variation.Modules linked in:
This patch adds the missing newline, fixing the output formatting.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
It seems that Cortex-A53 r0p4 added support for AIFSR and ADFSR, and
ID_MMFR0.AuxReg has been updated accordingly to report this fact. As
Cortex-A53 could be paired with CPUs which do not implement these
registers (e.g. all current revisions of Cortex-A57), this may trigger a
sanity check failure at boot.
The AuxReg value describes the availability of the ACTLR, AIFSR, and
ADFSR registers, which are only of use to 32-bit guest OSs, and have
IMPLEMENTATION DEFINED contents. Given the nature of these registers it
is likely that KVM will need to trap accesses regardless of whether the
CPUs are heterogeneous.
This patch masks out the ID_MMFR0.AuxReg value from the sanity checks,
preventing spurious warnings at boot time.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Andre Przywara <andre.przywara@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The only requirement the scheduler has on cluster IDs is that they must
be unique. When enumerating the topology based on MPIDR information the
kernel currently generates cluster IDs by using the first level of
affinity above the core ID (either level one or two depending on if the
core has multiple threads) however the ARMv8 architecture allows for up
to three levels of affinity. This means that an ARMv8 system may
contain cores which have MPIDRs identical other than affinity level
three which with current code will cause us to report multiple cores
with the same identification to the scheduler in violation of its
uniqueness requirement.
Ensure that we do not violate the scheduler requirements on systems that
uses all the affinity levels by incorporating both affinity levels two
and three into the cluser ID when the cores are not threaded.
While no currently known hardware uses multi-level clusters it is better
to program defensively, this will help ease bringup of systems that have
them and will ensure that things like distribution install media do not
need to be respun to replace kernels in order to deploy such systems.
In the worst case the system will work but perform suboptimally until a
kernel modified to handle the new topology better is installed, in the
best case this will be an adequate description of such topologies for
the scheduler to perform well.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Not all of the errata we have workarounds for apply necessarily to all
SoCs, so people compiling a kernel for one very specific SoC may not
need to patch the kernel.
Introduce a new submenu in the "Platform selection" menu to allow
people to turn off certain bugs if they are not affected. By default
all of them are enabled.
Normal users or distribution kernels shouldn't bother to deselect any
bugs here, since the alternatives framework will take care of
patching them in only if needed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[will: moved kconfig menu under `Kernel Features']
Signed-off-by: Will Deacon <will.deacon@arm.com>
The ARM erratum 832075 applies to certain revisions of Cortex-A57,
one of the workarounds is to change device loads into using
load-aquire semantics.
This is achieved using the alternatives framework.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The ARM errata 819472, 826319, 827319 and 824069 define the same
workaround for these hardware issues in certain Cortex-A53 parts.
Use the new alternatives framework and the CPU MIDR detection to
patch "cache clean" into "cache clean and invalidate" instructions if
an affected CPU is detected at runtime.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[will: add __maybe_unused to squash gcc warning]
Signed-off-by: Will Deacon <will.deacon@arm.com>
After each CPU has been started, we iterate through a list of
CPU features or bugs to detect CPUs which need (or could benefit
from) kernel code patches.
For each feature/bug there is a function which checks if that
particular CPU is affected. We will later provide some more generic
functions for common things like testing for certain MIDR ranges.
We do this for every CPU to cover big.LITTLE systems properly as
well.
If a certain feature/bug has been detected, the capability bit will
be set, so that later the call to apply_alternatives() will trigger
the actual code patching.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
With a blatant copy of some x86 bits we introduce the alternative
runtime patching "framework" to arm64.
This is quite basic for now and we only provide the functions we need
at this time.
This is connected to the newly introduced feature bits.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
For taking note if at least one CPU in the system needs a bug
workaround or would benefit from a code optimization, we create a new
bitmap to hold (artificial) feature bits.
Since elf_hwcap is part of the userland ABI, we keep it alone and
introduce a new data structure for that (along with some accessors).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
this patch adds missed resets property for CSR SiRFatlasVI SPI nodes.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
this patch adds missed resets property for CSR SiRFatlasVI Video Post
Processor(VPP) node.
Signed-off-by: Renwei Wu <renwei.wu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
this patch adds missed resets property for CSR SiRFprimaII Video Post
Processor(VPP) node.
Signed-off-by: Renwei Wu <renwei.wu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
this patch adds missed resets property for CSR SiRFprimaII GPS
related nodes.
Signed-off-by: Tao Huang <Tao.Huang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
The I2S controller can use the external clock as reference clock with
master mode. But based on different hardware or software design, this
external clock might be needed or not needed.
So the external input pin can be an independent pinctrl group, and the
card driver can decice to get it or not.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
The I2S controller can output mclk to external audio codec. But by
hardware design, some codecs need mclk and some codecs do not need
mclk. So the mclk pin can be an independent pinctrl group, and the
card driver can get it or not based on boards.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
we have done that for atlas6 in commit ed36c1a, 086b8904 etc. here we
do same things for prima2.
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
update_insn_emulation_mode() returns 0 on success, so we should be
treating any non-zero values as failure, rather than the other way
around. Otherwise, writes to the sysctl file controlling the emulation
are ignored and immediately rolled back.
Reported-by: Gene Hackmann <ghackmann@google.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
