linux-stable/arch/arm64/boot/dts/qcom/sm8450.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Linaro Limited
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <76800000>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 0>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_100>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 0>;
			L2_100: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_200>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 0>;
			L2_200: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_300>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 0>;
			L2_300: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_400>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 1>;
			L2_400: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_500>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 1>;
			L2_500: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_600>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 1>;
			L2_600: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo780";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_700>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 2>;
			#cooling-cells = <2>;
			clocks = <&cpufreq_hw 2>;
			L2_700: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

				core6 {
					cpu = <&CPU6>;
				};

				core7 {
					cpu = <&CPU7>;
				};
			};
		};

		idle-states {
			entry-method = "psci";

			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "silver-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <800>;
				exit-latency-us = <750>;
				min-residency-us = <4090>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "gold-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <600>;
				exit-latency-us = <1550>;
				min-residency-us = <4791>;
				local-timer-stop;
			};
		};

		domain-idle-states {
			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x41000044>;
				entry-latency-us = <1050>;
				exit-latency-us = <2500>;
				min-residency-us = <5309>;
			};

			CLUSTER_SLEEP_1: cluster-sleep-1 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x4100c344>;
				entry-latency-us = <2700>;
				exit-latency-us = <3500>;
				min-residency-us = <13959>;
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-sm8450", "qcom,scm";
			qcom,dload-mode = <&tcsr 0x13000>;
			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
			#reset-cells = <1>;
		};
	};

	clk_virt: interconnect-0 {
		compatible = "qcom,sm8450-clk-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect-1 {
		compatible = "qcom,sm8450-mc-virt";
		#interconnect-cells = <2>;
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	memory@a0000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0xa0000000 0x0 0x0>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
		};

		CPU_PD4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CPU_PD7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0>;
		};

		CLUSTER_PD: power-domain-cpu-cluster0 {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
		};
	};

	qup_opp_table_100mhz: opp-table-qup {
		compatible = "operating-points-v2";

		opp-50000000 {
			opp-hz = /bits/ 64 <50000000>;
			required-opps = <&rpmhpd_opp_min_svs>;
		};

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: memory@80000000 {
			reg = <0x0 0x80000000 0x0 0x600000>;
			no-map;
		};

		xbl_dt_log_mem: memory@80600000 {
			reg = <0x0 0x80600000 0x0 0x40000>;
			no-map;
		};

		xbl_ramdump_mem: memory@80640000 {
			reg = <0x0 0x80640000 0x0 0x180000>;
			no-map;
		};

		xbl_sc_mem: memory@807c0000 {
			reg = <0x0 0x807c0000 0x0 0x40000>;
			no-map;
		};

		aop_image_mem: memory@80800000 {
			reg = <0x0 0x80800000 0x0 0x60000>;
			no-map;
		};

		aop_cmd_db_mem: memory@80860000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x80860000 0x0 0x20000>;
			no-map;
		};

		aop_config_mem: memory@80880000 {
			reg = <0x0 0x80880000 0x0 0x20000>;
			no-map;
		};

		tme_crash_dump_mem: memory@808a0000 {
			reg = <0x0 0x808a0000 0x0 0x40000>;
			no-map;
		};

		tme_log_mem: memory@808e0000 {
			reg = <0x0 0x808e0000 0x0 0x4000>;
			no-map;
		};

		uefi_log_mem: memory@808e4000 {
			reg = <0x0 0x808e4000 0x0 0x10000>;
			no-map;
		};

		/* secdata region can be reused by apps */
		smem: memory@80900000 {
			compatible = "qcom,smem";
			reg = <0x0 0x80900000 0x0 0x200000>;
			hwlocks = <&tcsr_mutex 3>;
			no-map;
		};

		cpucp_fw_mem: memory@80b00000 {
			reg = <0x0 0x80b00000 0x0 0x100000>;
			no-map;
		};

		cdsp_secure_heap: memory@80c00000 {
			reg = <0x0 0x80c00000 0x0 0x4600000>;
			no-map;
		};

		video_mem: memory@85700000 {
			reg = <0x0 0x85700000 0x0 0x700000>;
			no-map;
		};

		adsp_mem: memory@85e00000 {
			reg = <0x0 0x85e00000 0x0 0x2100000>;
			no-map;
		};

		slpi_mem: memory@88000000 {
			reg = <0x0 0x88000000 0x0 0x1900000>;
			no-map;
		};

		cdsp_mem: memory@89900000 {
			reg = <0x0 0x89900000 0x0 0x2000000>;
			no-map;
		};

		ipa_fw_mem: memory@8b900000 {
			reg = <0x0 0x8b900000 0x0 0x10000>;
			no-map;
		};

		ipa_gsi_mem: memory@8b910000 {
			reg = <0x0 0x8b910000 0x0 0xa000>;
			no-map;
		};

		gpu_micro_code_mem: memory@8b91a000 {
			reg = <0x0 0x8b91a000 0x0 0x2000>;
			no-map;
		};

		spss_region_mem: memory@8ba00000 {
			reg = <0x0 0x8ba00000 0x0 0x180000>;
			no-map;
		};

		/* First part of the "SPU secure shared memory" region */
		spu_tz_shared_mem: memory@8bb80000 {
			reg = <0x0 0x8bb80000 0x0 0x60000>;
			no-map;
		};

		/* Second part of the "SPU secure shared memory" region */
		spu_modem_shared_mem: memory@8bbe0000 {
			reg = <0x0 0x8bbe0000 0x0 0x20000>;
			no-map;
		};

		mpss_mem: memory@8bc00000 {
			reg = <0x0 0x8bc00000 0x0 0x13200000>;
			no-map;
		};

		cvp_mem: memory@9ee00000 {
			reg = <0x0 0x9ee00000 0x0 0x700000>;
			no-map;
		};

		camera_mem: memory@9f500000 {
			reg = <0x0 0x9f500000 0x0 0x800000>;
			no-map;
		};

		rmtfs_mem: memory@9fd00000 {
			compatible = "qcom,rmtfs-mem";
			reg = <0x0 0x9fd00000 0x0 0x280000>;
			no-map;

			qcom,client-id = <1>;
			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
		};

		xbl_sc_mem2: memory@a6e00000 {
			reg = <0x0 0xa6e00000 0x0 0x40000>;
			no-map;
		};

		global_sync_mem: memory@a6f00000 {
			reg = <0x0 0xa6f00000 0x0 0x100000>;
			no-map;
		};

		/* uefi region can be reused by APPS */

		/* Linux kernel image is loaded at 0xa0000000 */

		oem_vm_mem: memory@bb000000 {
			reg = <0x0 0xbb000000 0x0 0x5000000>;
			no-map;
		};

		mte_mem: memory@c0000000 {
			reg = <0x0 0xc0000000 0x0 0x20000000>;
			no-map;
		};

		qheebsp_reserved_mem: memory@e0000000 {
			reg = <0x0 0xe0000000 0x0 0x600000>;
			no-map;
		};

		cpusys_vm_mem: memory@e0600000 {
			reg = <0x0 0xe0600000 0x0 0x400000>;
			no-map;
		};

		hyp_reserved_mem: memory@e0a00000 {
			reg = <0x0 0xe0a00000 0x0 0x100000>;
			no-map;
		};

		trust_ui_vm_mem: memory@e0b00000 {
			reg = <0x0 0xe0b00000 0x0 0x4af3000>;
			no-map;
		};

		trust_ui_vm_qrtr: memory@e55f3000 {
			reg = <0x0 0xe55f3000 0x0 0x9000>;
			no-map;
		};

		trust_ui_vm_vblk0_ring: memory@e55fc000 {
			reg = <0x0 0xe55fc000 0x0 0x4000>;
			no-map;
		};

		trust_ui_vm_swiotlb: memory@e5600000 {
			reg = <0x0 0xe5600000 0x0 0x100000>;
			no-map;
		};

		tz_stat_mem: memory@e8800000 {
			reg = <0x0 0xe8800000 0x0 0x100000>;
			no-map;
		};

		tags_mem: memory@e8900000 {
			reg = <0x0 0xe8900000 0x0 0x1200000>;
			no-map;
		};

		qtee_mem: memory@e9b00000 {
			reg = <0x0 0xe9b00000 0x0 0x500000>;
			no-map;
		};

		trusted_apps_mem: memory@ea000000 {
			reg = <0x0 0xea000000 0x0 0x3900000>;
			no-map;
		};

		trusted_apps_ext_mem: memory@ed900000 {
			reg = <0x0 0xed900000 0x0 0x3b00000>;
			no-map;
		};
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_LPASS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		smp2p_adsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_adsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_CDSP
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		smp2p_cdsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_cdsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_MPSS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		smp2p_modem_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_modem_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ipa_smp2p_out: ipa-ap-to-modem {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		ipa_smp2p_in: ipa-modem-to-ap {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-slpi {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_SLPI
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		smp2p_slpi_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_slpi_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sm8450";
			reg = <0x0 0x00100000 0x0 0x1f4200>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&sleep_clk>,
				 <&pcie0_phy>,
				 <&pcie1_phy>,
				 <0>,
				 <&ufs_mem_phy 0>,
				 <&ufs_mem_phy 1>,
				 <&ufs_mem_phy 2>,
				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
			clock-names = "bi_tcxo",
				      "sleep_clk",
				      "pcie_0_pipe_clk",
				      "pcie_1_pipe_clk",
				      "pcie_1_phy_aux_clk",
				      "ufs_phy_rx_symbol_0_clk",
				      "ufs_phy_rx_symbol_1_clk",
				      "ufs_phy_tx_symbol_0_clk",
				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		};

		gpi_dma2: dma-controller@800000 {
			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
			#dma-cells = <3>;
			reg = <0 0x00800000 0 0x60000>;
			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <12>;
			dma-channel-mask = <0x7e>;
			iommus = <&apps_smmu 0x496 0x0>;
			status = "disabled";
		};

		qupv3_id_2: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x008c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
			iommus = <&apps_smmu 0x483 0x0>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			i2c15: i2c@880000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00880000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c15_data_clk>;
				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi15: spi@880000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00880000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c16: i2c@884000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00884000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c16_data_clk>;
				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi16: spi@884000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00884000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c17: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00888000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c17_data_clk>;
				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi17: spi@888000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00888000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c18: i2c@88c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x0088c000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c18_data_clk>;
				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi18: spi@88c000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x0088c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c19: i2c@890000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00890000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c19_data_clk>;
				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi19: spi@890000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00890000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c20: i2c@894000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00894000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c20_data_clk>;
				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			uart20: serial@894000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00894000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart20_default>;
				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				status = "disabled";
			};

			spi20: spi@894000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00894000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c21: i2c@898000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00898000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c21_data_clk>;
				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi21: spi@898000 {
				compatible = "qcom,geni-spi";
				reg = <0 0x00898000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
				interconnect-names = "qup-core", "qup-config";
				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		gpi_dma0: dma-controller@900000 {
			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
			#dma-cells = <3>;
			reg = <0 0x00900000 0 0x60000>;
			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <12>;
			dma-channel-mask = <0x7e>;
			iommus = <&apps_smmu 0x5b6 0x0>;
			status = "disabled";
		};

		qupv3_id_0: geniqup@9c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x009c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			iommus = <&apps_smmu 0x5a3 0x0>;
			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
			interconnect-names = "qup-core";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			i2c0: i2c@980000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00980000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c0_data_clk>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi0: spi@980000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00980000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c1: i2c@984000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00984000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c1_data_clk>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi1: spi@984000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00984000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c2: i2c@988000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00988000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c2_data_clk>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi2: spi@988000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00988000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};


			i2c3: i2c@98c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x0098c000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c3_data_clk>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi3: spi@98c000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x0098c000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c4: i2c@990000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00990000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c4_data_clk>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi4: spi@990000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00990000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
				power-domains = <&rpmhpd RPMHPD_CX>;
				operating-points-v2 = <&qup_opp_table_100mhz>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c5: i2c@994000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00994000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c5_data_clk>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi5: spi@994000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00994000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};


			i2c6: i2c@998000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00998000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c6_data_clk>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi6: spi@998000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00998000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			uart7: serial@99c000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x0099c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
				interconnect-names = "qup-core",
						     "qup-config";
				status = "disabled";
			};
		};

		gpi_dma1: dma-controller@a00000 {
			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
			#dma-cells = <3>;
			reg = <0 0x00a00000 0 0x60000>;
			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <12>;
			dma-channel-mask = <0x7e>;
			iommus = <&apps_smmu 0x56 0x0>;
			status = "disabled";
		};

		qupv3_id_1: geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x00ac0000 0x0 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			iommus = <&apps_smmu 0x43 0x0>;
			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
			interconnect-names = "qup-core";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			i2c8: i2c@a80000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00a80000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c8_data_clk>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi8: spi@a80000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a80000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c9: i2c@a84000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00a84000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c9_data_clk>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi9: spi@a84000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a84000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c10: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00a88000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c10_data_clk>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi10: spi@a88000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a88000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c11: i2c@a8c000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00a8c000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c11_data_clk>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi11: spi@a8c000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a8c000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c12: i2c@a90000 {
				compatible = "qcom,geni-i2c";
				reg = <0x0 0x00a90000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c12_data_clk>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				status = "disabled";
			};

			spi12: spi@a90000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a90000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c13: i2c@a94000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a94000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c13_data_clk>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi13: spi@a94000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a94000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			i2c14: i2c@a98000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00a98000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c14_data_clk>;
				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};

			spi14: spi@a98000 {
				compatible = "qcom,geni-spi";
				reg = <0x0 0x00a98000 0x0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		rng: rng@10c3000 {
			compatible = "qcom,sm8450-trng", "qcom,trng";
			reg = <0 0x010c3000 0 0x1000>;
		};

		pcie0: pcie@1c00000 {
			compatible = "qcom,pcie-sm8450-pcie0";
			reg = <0 0x01c00000 0 0x3000>,
			      <0 0x60000000 0 0xf1d>,
			      <0 0x60000f20 0 0xa8>,
			      <0 0x60001000 0 0x1000>,
			      <0 0x60100000 0 0x100000>;
			reg-names = "parf", "dbi", "elbi", "atu", "config";
			device_type = "pci";
			linux,pci-domain = <0>;
			bus-range = <0x00 0xff>;
			num-lanes = <1>;

			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;

			msi-map = <0x0 &gic_its 0x5980 0x1>,
				  <0x100 &gic_its 0x5981 0x1>;
			msi-map-mask = <0xff00>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
				 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
				 <&pcie0_phy>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_PCIE_0_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
			clock-names = "pipe",
				      "pipe_mux",
				      "phy_pipe",
				      "ref",
				      "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "ddrss_sf_tbu",
				      "aggre0",
				      "aggre1";

			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
				    <0x100 &apps_smmu 0x1c01 0x1>;

			resets = <&gcc GCC_PCIE_0_BCR>;
			reset-names = "pci";

			power-domains = <&gcc PCIE_0_GDSC>;

			phys = <&pcie0_phy>;
			phy-names = "pciephy";

			perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
			wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&pcie0_default_state>;

			status = "disabled";
		};

		pcie0_phy: phy@1c06000 {
			compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
			reg = <0 0x01c06000 0 0x2000>;

			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_0_CLKREF_EN>,
				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe";

			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;

			#phy-cells = <0>;

			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			status = "disabled";
		};

		pcie1: pcie@1c08000 {
			compatible = "qcom,pcie-sm8450-pcie1";
			reg = <0 0x01c08000 0 0x3000>,
			      <0 0x40000000 0 0xf1d>,
			      <0 0x40000f20 0 0xa8>,
			      <0 0x40001000 0 0x1000>,
			      <0 0x40100000 0 0x100000>;
			reg-names = "parf", "dbi", "elbi", "atu", "config";
			device_type = "pci";
			linux,pci-domain = <1>;
			bus-range = <0x00 0xff>;
			num-lanes = <2>;

			#address-cells = <3>;
			#size-cells = <2>;

			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

			msi-map = <0x0 &gic_its 0x5a00 0x1>,
				  <0x100 &gic_its 0x5a01 0x1>;
			msi-map-mask = <0xff00>;
			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
				 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
				 <&pcie1_phy>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_PCIE_1_AUX_CLK>,
				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
			clock-names = "pipe",
				      "pipe_mux",
				      "phy_pipe",
				      "ref",
				      "aux",
				      "cfg",
				      "bus_master",
				      "bus_slave",
				      "slave_q2a",
				      "ddrss_sf_tbu",
				      "aggre1";

			iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
				    <0x100 &apps_smmu 0x1c81 0x1>;

			resets = <&gcc GCC_PCIE_1_BCR>;
			reset-names = "pci";

			power-domains = <&gcc PCIE_1_GDSC>;

			phys = <&pcie1_phy>;
			phy-names = "pciephy";

			perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
			wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;

			pinctrl-names = "default";
			pinctrl-0 = <&pcie1_default_state>;

			status = "disabled";
		};

		pcie1_phy: phy@1c0e000 {
			compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
			reg = <0 0x01c0e000 0 0x2000>;

			clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
				 <&gcc GCC_PCIE_1_CLKREF_EN>,
				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
				 <&gcc GCC_PCIE_1_PIPE_CLK>;
			clock-names = "aux",
				      "cfg_ahb",
				      "ref",
				      "rchng",
				      "pipe";

			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;

			#phy-cells = <0>;

			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
			reset-names = "phy";

			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
			assigned-clock-rates = <100000000>;

			status = "disabled";
		};

		config_noc: interconnect@1500000 {
			compatible = "qcom,sm8450-config-noc";
			reg = <0 0x01500000 0 0x1c000>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@1680000 {
			compatible = "qcom,sm8450-system-noc";
			reg = <0 0x01680000 0 0x1e200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		pcie_noc: interconnect@16c0000 {
			compatible = "qcom,sm8450-pcie-anoc";
			reg = <0 0x016c0000 0 0xe280>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre1_noc: interconnect@16e0000 {
			compatible = "qcom,sm8450-aggre1-noc";
			reg = <0 0x016e0000 0 0x1c080>;
			#interconnect-cells = <2>;
			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre2_noc: interconnect@1700000 {
			compatible = "qcom,sm8450-aggre2-noc";
			reg = <0 0x01700000 0 0x31080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
			clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&rpmhcc RPMH_IPA_CLK>;
		};

		mmss_noc: interconnect@1740000 {
			compatible = "qcom,sm8450-mmss-noc";
			reg = <0 0x01740000 0 0x1f080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x40000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1fc0000 {
			compatible = "qcom,sm8450-tcsr", "syscon";
			reg = <0x0 0x1fc0000 0x0 0x30000>;
		};

		gpu: gpu@3d00000 {
			compatible = "qcom,adreno-730.1", "qcom,adreno";
			reg = <0x0 0x03d00000 0x0 0x40000>,
			      <0x0 0x03d9e000 0x0 0x1000>,
			      <0x0 0x03d61000 0x0 0x800>;
			reg-names = "kgsl_3d0_reg_memory",
				    "cx_mem",
				    "cx_dbgc";

			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			iommus = <&adreno_smmu 0 0x400>,
				 <&adreno_smmu 1 0x400>;

			operating-points-v2 = <&gpu_opp_table>;

			qcom,gmu = <&gmu>;

			status = "disabled";

			zap-shader {
				memory-region = <&gpu_micro_code_mem>;
			};

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-818000000 {
					opp-hz = /bits/ 64 <818000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
				};

				opp-791000000 {
					opp-hz = /bits/ 64 <791000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
				};

				opp-734000000 {
					opp-hz = /bits/ 64 <734000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
				};

				opp-640000000 {
					opp-hz = /bits/ 64 <640000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
				};

				opp-599000000 {
					opp-hz = /bits/ 64 <599000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
				};

				opp-545000000 {
					opp-hz = /bits/ 64 <545000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
				};

				opp-492000000 {
					opp-hz = /bits/ 64 <492000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				opp-421000000 {
					opp-hz = /bits/ 64 <421000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
				};

				opp-350000000 {
					opp-hz = /bits/ 64 <350000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				opp-317000000 {
					opp-hz = /bits/ 64 <317000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};

				opp-285000000 {
					opp-hz = /bits/ 64 <285000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
				};

				opp-220000000 {
					opp-hz = /bits/ 64 <220000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
				};
			};
		};

		gmu: gmu@3d6a000 {
			compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
			reg = <0x0 0x03d6a000 0x0 0x35000>,
			      <0x0 0x03d50000 0x0 0x10000>,
			      <0x0 0x0b290000 0x0 0x10000>;
			reg-names = "gmu", "rscc", "gmu_pdc";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hfi", "gmu";

			clocks = <&gpucc GPU_CC_AHB_CLK>,
				 <&gpucc GPU_CC_CX_GMU_CLK>,
				 <&gpucc GPU_CC_CXO_CLK>,
				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
				 <&gpucc GPU_CC_DEMET_CLK>;
			clock-names = "ahb",
				      "gmu",
				      "cxo",
				      "axi",
				      "memnoc",
				      "hub",
				      "demet";

			power-domains = <&gpucc GPU_CX_GDSC>,
					<&gpucc GPU_GX_GDSC>;
			power-domain-names = "cx",
					     "gx";

			iommus = <&adreno_smmu 5 0x400>;

			qcom,qmp = <&aoss_qmp>;

			operating-points-v2 = <&gmu_opp_table>;

			gmu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-500000000 {
					opp-hz = /bits/ 64 <500000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
				};

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
				};
			};
		};

		gpucc: clock-controller@3d90000 {
			compatible = "qcom,sm8450-gpucc";
			reg = <0x0 0x03d90000 0x0 0xa000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		adreno_smmu: iommu@3da0000 {
			compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
				     "qcom,smmu-500", "arm,mmu-500";
			reg = <0x0 0x03da0000 0x0 0x40000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
				 <&gpucc GPU_CC_AHB_CLK>;
			clock-names = "gmu",
				      "hub",
				      "hlos",
				      "bus",
				      "iface",
				      "ahb";
			power-domains = <&gpucc GPU_CX_GDSC>;
			dma-coherent;
		};

		usb_1_hsphy: phy@88e3000 {
			compatible = "qcom,sm8450-usb-hs-phy",
				     "qcom,usb-snps-hs-7nm-phy";
			reg = <0 0x088e3000 0 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		};

		usb_1_qmpphy: phy@88e8000 {
			compatible = "qcom,sm8450-qmp-usb3-dp-phy";
			reg = <0 0x088e8000 0 0x3000>;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
			clock-names = "aux", "ref", "com_aux", "usb3_pipe";

			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <1>;
			#phy-cells = <1>;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;

					usb_1_qmpphy_out: endpoint {
					};
				};

				port@1 {
					reg = <1>;

					usb_1_qmpphy_usb_ss_in: endpoint {
					};
				};

				port@2 {
					reg = <2>;

					usb_1_qmpphy_dp_in: endpoint {
					};
				};
			};
		};

		remoteproc_slpi: remoteproc@2400000 {
			compatible = "qcom,sm8450-slpi-pas";
			reg = <0 0x02400000 0 0x4000>;

			interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_LCX>,
					<&rpmhpd RPMHPD_LMX>;
			power-domain-names = "lcx", "lmx";

			memory-region = <&slpi_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_slpi_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_SLPI
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "slpi";
				qcom,remote-pid = <3>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "sdsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x0541 0x0>;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x0542 0x0>;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x0543 0x0>;
						/* note: shared-cb = <4> in downstream */
					};
				};
			};
		};

		wsa2macro: codec@31e0000 {
			compatible = "qcom,sm8450-lpass-wsa-macro";
			reg = <0 0x031e0000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&vamacro>;
			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			#clock-cells = <0>;
			clock-output-names = "wsa2-mclk";
			#sound-dai-cells = <1>;
		};

		swr4: soundwire@31f0000 {
			compatible = "qcom,soundwire-v1.7.0";
			reg = <0 0x031f0000 0 0x2000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&wsa2macro>;
			clock-names = "iface";
			label = "WSA2";

			pinctrl-0 = <&wsa2_swr_active>;
			pinctrl-names = "default";

			qcom,din-ports = <2>;
			qcom,dout-ports = <6>;

			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		rxmacro: codec@3200000 {
			compatible = "qcom,sm8450-lpass-rx-macro";
			reg = <0 0x03200000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&vamacro>;
			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
		};

		swr1: soundwire@3210000 {
			compatible = "qcom,soundwire-v1.7.0";
			reg = <0 0x03210000 0 0x2000>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rxmacro>;
			clock-names = "iface";
			label = "RX";
			qcom,din-ports = <0>;
			qcom,dout-ports = <5>;

			pinctrl-0 = <&rx_swr_active>;
			pinctrl-names = "default";

			qcom,ports-sinterval-low =	/bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		txmacro: codec@3220000 {
			compatible = "qcom,sm8450-lpass-tx-macro";
			reg = <0 0x03220000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&vamacro>;
			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
		};

		wsamacro: codec@3240000 {
			compatible = "qcom,sm8450-lpass-wsa-macro";
			reg = <0 0x03240000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&vamacro>;
			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";

			#clock-cells = <0>;
			clock-output-names = "mclk";
			#sound-dai-cells = <1>;
		};

		swr0: soundwire@3250000 {
			compatible = "qcom,soundwire-v1.7.0";
			reg = <0 0x03250000 0 0x2000>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&wsamacro>;
			clock-names = "iface";
			label = "WSA";

			pinctrl-0 = <&wsa_swr_active>;
			pinctrl-names = "default";

			qcom,din-ports = <2>;
			qcom,dout-ports = <6>;

			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		swr2: soundwire@33b0000 {
			compatible = "qcom,soundwire-v1.7.0";
			reg = <0 0x033b0000 0 0x2000>;
			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "core", "wakeup";

			clocks = <&txmacro>;
			clock-names = "iface";
			label = "TX";

			pinctrl-0 = <&tx_swr_active>;
			pinctrl-names = "default";

			qcom,din-ports = <4>;
			qcom,dout-ports = <0>;
			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x01 0x03 0x03>;
			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x01 0x01>;
			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;
			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;
			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;
			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff>;
			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;
			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;
			qcom,ports-lane-control =	/bits/ 8 <0x01 0x02 0x00 0x00>;

			#address-cells = <2>;
			#size-cells = <0>;
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		vamacro: codec@33f0000 {
			compatible = "qcom,sm8450-lpass-va-macro";
			reg = <0 0x033f0000 0 0x1000>;
			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
			clock-names = "mclk", "macro", "dcodec", "npl";

			#clock-cells = <0>;
			clock-output-names = "fsgen";
			#sound-dai-cells = <1>;
			status = "disabled";
		};

		remoteproc_adsp: remoteproc@30000000 {
			compatible = "qcom,sm8450-adsp-pas";
			reg = <0 0x30000000 0 0x100>;

			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_LCX>,
					<&rpmhpd RPMHPD_LMX>;
			power-domain-names = "lcx", "lmx";

			memory-region = <&adsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_adsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			remoteproc_adsp_glink: glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_LPASS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "lpass";
				qcom,remote-pid = <2>;

				gpr {
					compatible = "qcom,gpr";
					qcom,glink-channels = "adsp_apps";
					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
					qcom,intents = <512 20>;
					#address-cells = <1>;
					#size-cells = <0>;

					q6apm: service@1 {
						compatible = "qcom,q6apm";
						reg = <GPR_APM_MODULE_IID>;
						#sound-dai-cells = <0>;
						qcom,protection-domain = "avs/audio",
									 "msm/adsp/audio_pd";

						q6apmdai: dais {
							compatible = "qcom,q6apm-dais";
							iommus = <&apps_smmu 0x1801 0x0>;
						};

						q6apmbedai: bedais {
							compatible = "qcom,q6apm-lpass-dais";
							#sound-dai-cells = <1>;
						};
					};

					q6prm: service@2 {
						compatible = "qcom,q6prm";
						reg = <GPR_PRM_MODULE_IID>;
						qcom,protection-domain = "avs/audio",
									 "msm/adsp/audio_pd";

						q6prmcc: clock-controller {
							compatible = "qcom,q6prm-lpass-clocks";
							#clock-cells = <2>;
						};
					};
				};

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "adsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1803 0x0>;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1804 0x0>;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1805 0x0>;
					};
				};
			};
		};

		remoteproc_cdsp: remoteproc@32300000 {
			compatible = "qcom,sm8450-cdsp-pas";
			reg = <0 0x32300000 0 0x1400000>;

			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>,
					<&rpmhpd RPMHPD_MXC>;
			power-domain-names = "cx", "mxc";

			memory-region = <&cdsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_cdsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_CDSP
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "cdsp";
				qcom,remote-pid = <5>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "cdsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x2161 0x0400>,
							 <&apps_smmu 0x1021 0x1420>;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x2162 0x0400>,
							 <&apps_smmu 0x1022 0x1420>;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x2163 0x0400>,
							 <&apps_smmu 0x1023 0x1420>;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x2164 0x0400>,
							 <&apps_smmu 0x1024 0x1420>;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x2165 0x0400>,
							 <&apps_smmu 0x1025 0x1420>;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x2166 0x0400>,
							 <&apps_smmu 0x1026 0x1420>;
					};

					compute-cb@7 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <7>;
						iommus = <&apps_smmu 0x2167 0x0400>,
							 <&apps_smmu 0x1027 0x1420>;
					};

					compute-cb@8 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <8>;
						iommus = <&apps_smmu 0x2168 0x0400>,
							 <&apps_smmu 0x1028 0x1420>;
					};

					/* note: secure cb9 in downstream */
				};
			};
		};

		remoteproc_mpss: remoteproc@4080000 {
			compatible = "qcom,sm8450-mpss-pas";
			reg = <0x0 0x04080000 0x0 0x4040>;

			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover",
					  "stop-ack", "shutdown-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd RPMHPD_CX>,
					<&rpmhpd RPMHPD_MSS>;
			power-domain-names = "cx", "mss";

			memory-region = <&mpss_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_modem_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_MPSS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;
				label = "modem";
				qcom,remote-pid = <1>;
			};
		};

		videocc: clock-controller@aaf0000 {
			compatible = "qcom,sm8450-videocc";
			reg = <0 0x0aaf0000 0 0x10000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_VIDEO_AHB_CLK>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			required-opps = <&rpmhpd_opp_low_svs>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		cci0: cci@ac15000 {
			compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
			reg = <0 0x0ac15000 0 0x1000>;
			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
			power-domains = <&camcc TITAN_TOP_GDSC>;

			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
				 <&camcc CAM_CC_CPAS_AHB_CLK>,
				 <&camcc CAM_CC_CCI_0_CLK>,
				 <&camcc CAM_CC_CCI_0_CLK_SRC>;
			clock-names = "camnoc_axi",
				      "slow_ahb_src",
				      "cpas_ahb",
				      "cci",
				      "cci_src";
			pinctrl-0 = <&cci0_default &cci1_default>;
			pinctrl-1 = <&cci0_sleep &cci1_sleep>;
			pinctrl-names = "default", "sleep";

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;

			cci0_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cci0_i2c1: i2c-bus@1 {
				reg = <1>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		cci1: cci@ac16000 {
			compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
			reg = <0 0x0ac16000 0 0x1000>;
			interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
			power-domains = <&camcc TITAN_TOP_GDSC>;

			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
				 <&camcc CAM_CC_CPAS_AHB_CLK>,
				 <&camcc CAM_CC_CCI_1_CLK>,
				 <&camcc CAM_CC_CCI_1_CLK_SRC>;
			clock-names = "camnoc_axi",
				      "slow_ahb_src",
				      "cpas_ahb",
				      "cci",
				      "cci_src";
			pinctrl-0 = <&cci2_default &cci3_default>;
			pinctrl-1 = <&cci2_sleep &cci3_sleep>;
			pinctrl-names = "default", "sleep";

			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;

			cci1_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cci1_i2c1: i2c-bus@1 {
				reg = <1>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		camcc: clock-controller@ade0000 {
			compatible = "qcom,sm8450-camcc";
			reg = <0 0x0ade0000 0 0x20000>;
			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			required-opps = <&rpmhpd_opp_low_svs>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			status = "disabled";
		};

		mdss: display-subsystem@ae00000 {
			compatible = "qcom,sm8450-mdss";
			reg = <0 0x0ae00000 0 0x1000>;
			reg-names = "mdss";

			/* same path used twice */
			interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
					<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
			interconnect-names = "mdp0-mem",
					     "mdp1-mem",
					     "cpu-cfg";

			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

			power-domains = <&dispcc MDSS_GDSC>;

			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
				 <&gcc GCC_DISP_HF_AXI_CLK>,
				 <&gcc GCC_DISP_SF_AXI_CLK>,
				 <&dispcc DISP_CC_MDSS_MDP_CLK>;

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;

			iommus = <&apps_smmu 0x2800 0x402>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@ae01000 {
				compatible = "qcom,sm8450-dpu";
				reg = <0 0x0ae01000 0 0x8f000>,
				      <0 0x0aeb0000 0 0x2008>;
				reg-names = "mdp", "vbif";

				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
					<&gcc GCC_DISP_SF_AXI_CLK>,
					<&dispcc DISP_CC_MDSS_AHB_CLK>,
					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
					<&dispcc DISP_CC_MDSS_MDP_CLK>,
					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				clock-names = "bus",
					      "nrt_bus",
					      "iface",
					      "lut",
					      "core",
					      "vsync";

				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				assigned-clock-rates = <19200000>;

				operating-points-v2 = <&mdp_opp_table>;
				power-domains = <&rpmhpd RPMHPD_MMCX>;

				interrupt-parent = <&mdss>;
				interrupts = <0>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						dpu_intf1_out: endpoint {
							remote-endpoint = <&mdss_dsi0_in>;
						};
					};

					port@1 {
						reg = <1>;
						dpu_intf2_out: endpoint {
							remote-endpoint = <&mdss_dsi1_in>;
						};
					};

					port@2 {
						reg = <2>;
						dpu_intf0_out: endpoint {
							remote-endpoint = <&mdss_dp0_in>;
						};
					};
				};

				mdp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-172000000 {
						opp-hz = /bits/ 64 <172000000>;
						required-opps = <&rpmhpd_opp_low_svs_d1>;
					};

					opp-200000000 {
						opp-hz = /bits/ 64 <200000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-325000000 {
						opp-hz = /bits/ 64 <325000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-375000000 {
						opp-hz = /bits/ 64 <375000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};

					opp-500000000 {
						opp-hz = /bits/ 64 <500000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};
				};
			};

			mdss_dp0: displayport-controller@ae90000 {
				compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
				reg = <0 0xae90000 0 0x200>,
				      <0 0xae90200 0 0x200>,
				      <0 0xae90400 0 0xc00>,
				      <0 0xae91000 0 0x400>,
				      <0 0xae91400 0 0x400>;
				interrupt-parent = <&mdss>;
				interrupts = <12>;
				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
				clock-names = "core_iface",
					      "core_aux",
					      "ctrl_link",
					      "ctrl_link_iface",
					      "stream_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
				phy-names = "dp";

				#sound-dai-cells = <0>;

				operating-points-v2 = <&dp_opp_table>;
				power-domains = <&rpmhpd RPMHPD_MMCX>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_dp0_in: endpoint {
							remote-endpoint = <&dpu_intf0_out>;
						};
					};
				};

				dp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-160000000 {
						opp-hz = /bits/ 64 <160000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-270000000 {
						opp-hz = /bits/ 64 <270000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-540000000 {
						opp-hz = /bits/ 64 <540000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};

					opp-810000000 {
						opp-hz = /bits/ 64 <810000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};
				};
			};

			mdss_dsi0: dsi@ae94000 {
				compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0 0x0ae94000 0 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4>;

				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					<&gcc GCC_DISP_HF_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";

				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;

				operating-points-v2 = <&mdss_dsi_opp_table>;
				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&mdss_dsi0_phy>;
				phy-names = "dsi";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_dsi0_in: endpoint {
							remote-endpoint = <&dpu_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;
						mdss_dsi0_out: endpoint {
						};
					};
				};

				mdss_dsi_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-187500000 {
						opp-hz = /bits/ 64 <187500000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-300000000 {
						opp-hz = /bits/ 64 <300000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-358000000 {
						opp-hz = /bits/ 64 <358000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};
				};
			};

			mdss_dsi0_phy: phy@ae94400 {
				compatible = "qcom,sm8450-dsi-phy-5nm";
				reg = <0 0x0ae94400 0 0x200>,
				      <0 0x0ae94600 0 0x280>,
				      <0 0x0ae94900 0 0x260>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&rpmhcc RPMH_CXO_CLK>;
				clock-names = "iface", "ref";

				status = "disabled";
			};

			mdss_dsi1: dsi@ae96000 {
				compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0 0x0ae96000 0 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <5>;

				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&gcc GCC_DISP_HF_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";

				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;

				operating-points-v2 = <&mdss_dsi_opp_table>;
				power-domains = <&rpmhpd RPMHPD_MMCX>;

				phys = <&mdss_dsi1_phy>;
				phy-names = "dsi";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdss_dsi1_in: endpoint {
							remote-endpoint = <&dpu_intf2_out>;
						};
					};

					port@1 {
						reg = <1>;
						mdss_dsi1_out: endpoint {
						};
					};
				};
			};

			mdss_dsi1_phy: phy@ae96400 {
				compatible = "qcom,sm8450-dsi-phy-5nm";
				reg = <0 0x0ae96400 0 0x200>,
				      <0 0x0ae96600 0 0x280>,
				      <0 0x0ae96900 0 0x260>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&rpmhcc RPMH_CXO_CLK>;
				clock-names = "iface", "ref";

				status = "disabled";
			};
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,sm8450-dispcc";
			reg = <0 0x0af00000 0 0x20000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&gcc GCC_DISP_AHB_CLK>,
				 <&sleep_clk>,
				 <&mdss_dsi0_phy 0>,
				 <&mdss_dsi0_phy 1>,
				 <&mdss_dsi1_phy 0>,
				 <&mdss_dsi1_phy 1>,
				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
				 <0>, /* dp1 */
				 <0>,
				 <0>, /* dp2 */
				 <0>,
				 <0>, /* dp3 */
				 <0>;
			power-domains = <&rpmhpd RPMHPD_MMCX>;
			required-opps = <&rpmhpd_opp_low_svs>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			status = "disabled";
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,sm8450-pdc", "qcom,pdc";
			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
			qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
					  <94 609 31>, <125 63 1>, <126 716 12>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		tsens0: thermal-sensor@c263000 {
			compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
			reg = <0 0x0c263000 0 0x1000>, /* TM */
			      <0 0x0c222000 0 0x1000>; /* SROT */
			#qcom,sensors = <16>;
			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal-sensor@c265000 {
			compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
			reg = <0 0x0c265000 0 0x1000>, /* TM */
			      <0 0x0c223000 0 0x1000>; /* SROT */
			#qcom,sensors = <16>;
			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		aoss_qmp: power-management@c300000 {
			compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
			reg = <0 0x0c300000 0 0x400>;
			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
						     IRQ_TYPE_EDGE_RISING>;
			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;

			#clock-cells = <0>;
		};

		sram@c3f0000 {
			compatible = "qcom,rpmh-stats";
			reg = <0 0x0c3f0000 0 0x400>;
		};

		spmi_bus: spmi@c400000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0 0x0c400000 0 0x00003000>,
			      <0 0x0c500000 0 0x00400000>,
			      <0 0x0c440000 0 0x00080000>,
			      <0 0x0c4c0000 0 0x00010000>,
			      <0 0x0c42d000 0 0x00010000>;
			reg-names = "core",
				    "chnls",
				    "obsrvr",
				    "intr",
				    "cnfg";
			interrupt-names = "periph_irq";
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			#address-cells = <2>;
			#size-cells = <0>;
		};

		ipcc: mailbox@ed18000 {
			compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
			reg = <0 0x0ed18000 0 0x1000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#mbox-cells = <2>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sm8450-tlmm";
			reg = <0 0x0f100000 0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 211>;
			wakeup-parent = <&pdc>;

			sdc2_default_state: sdc2-default-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <16>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <16>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <16>;
					bias-pull-up;
				};
			};

			sdc2_sleep_state: sdc2-sleep-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <2>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <2>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			cci0_default: cci0-default-state {
				/* SDA, SCL */
				pins = "gpio110", "gpio111";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci0_sleep: cci0-sleep-state {
				/* SDA, SCL */
				pins = "gpio110", "gpio111";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			cci1_default: cci1-default-state {
				/* SDA, SCL */
				pins = "gpio112", "gpio113";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci1_sleep: cci1-sleep-state {
				/* SDA, SCL */
				pins = "gpio112", "gpio113";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			cci2_default: cci2-default-state {
				/* SDA, SCL */
				pins = "gpio114", "gpio115";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci2_sleep: cci2-sleep-state {
				/* SDA, SCL */
				pins = "gpio114", "gpio115";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			cci3_default: cci3-default-state {
				/* SDA, SCL */
				pins = "gpio208", "gpio209";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci3_sleep: cci3-sleep-state {
				/* SDA, SCL */
				pins = "gpio208", "gpio209";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			pcie0_default_state: pcie0-default-state {
				perst-pins {
					pins = "gpio94";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

				clkreq-pins {
					pins = "gpio95";
					function = "pcie0_clkreqn";
					drive-strength = <2>;
					bias-pull-up;
				};

				wake-pins {
					pins = "gpio96";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			pcie1_default_state: pcie1-default-state {
				perst-pins {
					pins = "gpio97";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-down;
				};

				clkreq-pins {
					pins = "gpio98";
					function = "pcie1_clkreqn";
					drive-strength = <2>;
					bias-pull-up;
				};

				wake-pins {
					pins = "gpio99";
					function = "gpio";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
				pins = "gpio0", "gpio1";
				function = "qup0";
			};

			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
				pins = "gpio4", "gpio5";
				function = "qup1";
			};

			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
				pins = "gpio8", "gpio9";
				function = "qup2";
			};

			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
				pins = "gpio12", "gpio13";
				function = "qup3";
			};

			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
				pins = "gpio16", "gpio17";
				function = "qup4";
			};

			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
				pins = "gpio206", "gpio207";
				function = "qup5";
			};

			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
				pins = "gpio20", "gpio21";
				function = "qup6";
			};

			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
				pins = "gpio28", "gpio29";
				function = "qup8";
			};

			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
				pins = "gpio32", "gpio33";
				function = "qup9";
			};

			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
				pins = "gpio36", "gpio37";
				function = "qup10";
			};

			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
				pins = "gpio40", "gpio41";
				function = "qup11";
			};

			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
				pins = "gpio44", "gpio45";
				function = "qup12";
			};

			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
				pins = "gpio48", "gpio49";
				function = "qup13";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c14_data_clk: qup-i2c14-data-clk-state {
				pins = "gpio52", "gpio53";
				function = "qup14";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
				pins = "gpio56", "gpio57";
				function = "qup15";
			};

			qup_i2c16_data_clk: qup-i2c16-data-clk-state {
				pins = "gpio60", "gpio61";
				function = "qup16";
			};

			qup_i2c17_data_clk: qup-i2c17-data-clk-state {
				pins = "gpio64", "gpio65";
				function = "qup17";
			};

			qup_i2c18_data_clk: qup-i2c18-data-clk-state {
				pins = "gpio68", "gpio69";
				function = "qup18";
			};

			qup_i2c19_data_clk: qup-i2c19-data-clk-state {
				pins = "gpio72", "gpio73";
				function = "qup19";
			};

			qup_i2c20_data_clk: qup-i2c20-data-clk-state {
				pins = "gpio76", "gpio77";
				function = "qup20";
			};

			qup_i2c21_data_clk: qup-i2c21-data-clk-state {
				pins = "gpio80", "gpio81";
				function = "qup21";
			};

			qup_spi0_cs: qup-spi0-cs-state {
				pins = "gpio3";
				function = "qup0";
			};

			qup_spi0_data_clk: qup-spi0-data-clk-state {
				pins = "gpio0", "gpio1", "gpio2";
				function = "qup0";
			};

			qup_spi1_cs: qup-spi1-cs-state {
				pins = "gpio7";
				function = "qup1";
			};

			qup_spi1_data_clk: qup-spi1-data-clk-state {
				pins = "gpio4", "gpio5", "gpio6";
				function = "qup1";
			};

			qup_spi2_cs: qup-spi2-cs-state {
				pins = "gpio11";
				function = "qup2";
			};

			qup_spi2_data_clk: qup-spi2-data-clk-state {
				pins = "gpio8", "gpio9", "gpio10";
				function = "qup2";
			};

			qup_spi3_cs: qup-spi3-cs-state {
				pins = "gpio15";
				function = "qup3";
			};

			qup_spi3_data_clk: qup-spi3-data-clk-state {
				pins = "gpio12", "gpio13", "gpio14";
				function = "qup3";
			};

			qup_spi4_cs: qup-spi4-cs-state {
				pins = "gpio19";
				function = "qup4";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi4_data_clk: qup-spi4-data-clk-state {
				pins = "gpio16", "gpio17", "gpio18";
				function = "qup4";
			};

			qup_spi5_cs: qup-spi5-cs-state {
				pins = "gpio85";
				function = "qup5";
			};

			qup_spi5_data_clk: qup-spi5-data-clk-state {
				pins = "gpio206", "gpio207", "gpio84";
				function = "qup5";
			};

			qup_spi6_cs: qup-spi6-cs-state {
				pins = "gpio23";
				function = "qup6";
			};

			qup_spi6_data_clk: qup-spi6-data-clk-state {
				pins = "gpio20", "gpio21", "gpio22";
				function = "qup6";
			};

			qup_spi8_cs: qup-spi8-cs-state {
				pins = "gpio31";
				function = "qup8";
			};

			qup_spi8_data_clk: qup-spi8-data-clk-state {
				pins = "gpio28", "gpio29", "gpio30";
				function = "qup8";
			};

			qup_spi9_cs: qup-spi9-cs-state {
				pins = "gpio35";
				function = "qup9";
			};

			qup_spi9_data_clk: qup-spi9-data-clk-state {
				pins = "gpio32", "gpio33", "gpio34";
				function = "qup9";
			};

			qup_spi10_cs: qup-spi10-cs-state {
				pins = "gpio39";
				function = "qup10";
			};

			qup_spi10_data_clk: qup-spi10-data-clk-state {
				pins = "gpio36", "gpio37", "gpio38";
				function = "qup10";
			};

			qup_spi11_cs: qup-spi11-cs-state {
				pins = "gpio43";
				function = "qup11";
			};

			qup_spi11_data_clk: qup-spi11-data-clk-state {
				pins = "gpio40", "gpio41", "gpio42";
				function = "qup11";
			};

			qup_spi12_cs: qup-spi12-cs-state {
				pins = "gpio47";
				function = "qup12";
			};

			qup_spi12_data_clk: qup-spi12-data-clk-state {
				pins = "gpio44", "gpio45", "gpio46";
				function = "qup12";
			};

			qup_spi13_cs: qup-spi13-cs-state {
				pins = "gpio51";
				function = "qup13";
			};

			qup_spi13_data_clk: qup-spi13-data-clk-state {
				pins = "gpio48", "gpio49", "gpio50";
				function = "qup13";
			};

			qup_spi14_cs: qup-spi14-cs-state {
				pins = "gpio55";
				function = "qup14";
			};

			qup_spi14_data_clk: qup-spi14-data-clk-state {
				pins = "gpio52", "gpio53", "gpio54";
				function = "qup14";
			};

			qup_spi15_cs: qup-spi15-cs-state {
				pins = "gpio59";
				function = "qup15";
			};

			qup_spi15_data_clk: qup-spi15-data-clk-state {
				pins = "gpio56", "gpio57", "gpio58";
				function = "qup15";
			};

			qup_spi16_cs: qup-spi16-cs-state {
				pins = "gpio63";
				function = "qup16";
			};

			qup_spi16_data_clk: qup-spi16-data-clk-state {
				pins = "gpio60", "gpio61", "gpio62";
				function = "qup16";
			};

			qup_spi17_cs: qup-spi17-cs-state {
				pins = "gpio67";
				function = "qup17";
			};

			qup_spi17_data_clk: qup-spi17-data-clk-state {
				pins = "gpio64", "gpio65", "gpio66";
				function = "qup17";
			};

			qup_spi18_cs: qup-spi18-cs-state {
				pins = "gpio71";
				function = "qup18";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi18_data_clk: qup-spi18-data-clk-state {
				pins = "gpio68", "gpio69", "gpio70";
				function = "qup18";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi19_cs: qup-spi19-cs-state {
				pins = "gpio75";
				function = "qup19";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi19_data_clk: qup-spi19-data-clk-state {
				pins = "gpio72", "gpio73", "gpio74";
				function = "qup19";
				drive-strength = <6>;
				bias-disable;
			};

			qup_spi20_cs: qup-spi20-cs-state {
				pins = "gpio79";
				function = "qup20";
			};

			qup_spi20_data_clk: qup-spi20-data-clk-state {
				pins = "gpio76", "gpio77", "gpio78";
				function = "qup20";
			};

			qup_spi21_cs: qup-spi21-cs-state {
				pins = "gpio83";
				function = "qup21";
			};

			qup_spi21_data_clk: qup-spi21-data-clk-state {
				pins = "gpio80", "gpio81", "gpio82";
				function = "qup21";
			};

			qup_uart7_rx: qup-uart7-rx-state {
				pins = "gpio26";
				function = "qup7";
				drive-strength = <2>;
				bias-disable;
			};

			qup_uart7_tx: qup-uart7-tx-state {
				pins = "gpio27";
				function = "qup7";
				drive-strength = <2>;
				bias-disable;
			};

			qup_uart20_default: qup-uart20-default-state {
				pins = "gpio76", "gpio77", "gpio78", "gpio79";
				function = "qup20";
			};
		};

		lpass_tlmm: pinctrl@3440000 {
			compatible = "qcom,sm8450-lpass-lpi-pinctrl";
			reg = <0 0x03440000 0x0 0x20000>,
			      <0 0x034d0000 0x0 0x10000>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&lpass_tlmm 0 0 23>;

			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
			clock-names = "core", "audio";

			tx_swr_active: tx-swr-active-state {
				clk-pins {
					pins = "gpio0";
					function = "swr_tx_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio1", "gpio2", "gpio14";
					function = "swr_tx_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			rx_swr_active: rx-swr-active-state {
				clk-pins {
					pins = "gpio3";
					function = "swr_rx_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio4", "gpio5";
					function = "swr_rx_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			dmic01_default: dmic01-default-state {
				clk-pins {
					pins = "gpio6";
					function = "dmic1_clk";
					drive-strength = <8>;
					output-high;
				};

				data-pins {
					pins = "gpio7";
					function = "dmic1_data";
					drive-strength = <8>;
				};
			};

			dmic02_default: dmic02-default-state {
				clk-pins {
					pins = "gpio8";
					function = "dmic2_clk";
					drive-strength = <8>;
					output-high;
				};

				data-pins {
					pins = "gpio9";
					function = "dmic2_data";
					drive-strength = <8>;
				};
			};

			wsa_swr_active: wsa-swr-active-state {
				clk-pins {
					pins = "gpio10";
					function = "wsa_swr_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio11";
					function = "wsa_swr_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};

			wsa2_swr_active: wsa2-swr-active-state {
				clk-pins {
					pins = "gpio15";
					function = "wsa2_swr_clk";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-disable;
				};

				data-pins {
					pins = "gpio16";
					function = "wsa2_swr_data";
					drive-strength = <2>;
					slew-rate = <1>;
					bias-bus-hold;
				};
			};
		};

		sram@146aa000 {
			compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
			reg = <0 0x146aa000 0 0x1000>;
			ranges = <0 0 0x146aa000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;

			pil-reloc@94c {
				compatible = "qcom,pil-reloc-info";
				reg = <0x94c 0xc8>;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
			reg = <0 0x15000000 0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17100000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x40000>;
			reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			gic_its: msi-controller@17140000 {
				compatible = "arm,gic-v3-its";
				reg = <0x0 0x17140000 0x0 0x20000>;
				msi-controller;
				#msi-cells = <1>;
			};
		};

		timer@17420000 {
			compatible = "arm,armv7-timer-mem";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0 0x20000000>;
			reg = <0x0 0x17420000 0x0 0x1000>;
			clock-frequency = <19200000>;

			frame@17421000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17421000 0x1000>,
				      <0x17422000 0x1000>;
			};

			frame@17423000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17423000 0x1000>;
				status = "disabled";
			};

			frame@17425000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17425000 0x1000>;
				status = "disabled";
			};

			frame@17427000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17427000 0x1000>;
				status = "disabled";
			};

			frame@17429000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17429000 0x1000>;
				status = "disabled";
			};

			frame@1742b000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x1742b000 0x1000>;
				status = "disabled";
			};

			frame@1742d000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x1742d000 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@17a00000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x0 0x17a00000 0x0 0x10000>,
			      <0x0 0x17a10000 0x0 0x10000>,
			      <0x0 0x17a20000 0x0 0x10000>,
			      <0x0 0x17a30000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
					  <WAKE_TCS    2>, <CONTROL_TCS 0>;
			power-domains = <&CLUSTER_PD>;

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: clock-controller {
				compatible = "qcom,sm8450-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sm8450-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs_d1: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
					};

					rpmhpd_opp_low_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_low_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
					};

					rpmhpd_opp_svs: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l0: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
					};

					rpmhpd_opp_svs_l1: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_svs_l2: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
					};

					rpmhpd_opp_nom: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp11 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp12 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp13 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp14 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};
		};

		cpufreq_hw: cpufreq@17d91000 {
			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
			reg = <0 0x17d91000 0 0x1000>,
			      <0 0x17d92000 0 0x1000>,
			      <0 0x17d93000 0 0x1000>;
			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
			clock-names = "xo", "alternate";
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
			#freq-domain-cells = <1>;
			#clock-cells = <1>;
		};

		gem_noc: interconnect@19100000 {
			compatible = "qcom,sm8450-gem-noc";
			reg = <0 0x19100000 0 0xbb800>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system-cache-controller@19200000 {
			compatible = "qcom,sm8450-llcc";
			reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
			      <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
			      <0 0x19a00000 0 0x80000>;
			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
				    "llcc3_base", "llcc_broadcast_base";
			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		};

		ufs_mem_hc: ufshc@1d84000 {
			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
				     "jedec,ufs-2.0";
			reg = <0 0x01d84000 0 0x3000>;
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufs_mem_phy>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			#reset-cells = <1>;
			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			power-domains = <&gcc UFS_PHY_GDSC>;

			iommus = <&apps_smmu 0xe0 0x0>;
			dma-coherent;

			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
			interconnect-names = "ufs-ddr", "cpu-ufs";
			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk";
			clocks =
				<&gcc GCC_UFS_PHY_AXI_CLK>,
				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				<&gcc GCC_UFS_PHY_AHB_CLK>,
				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				<&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
			freq-table-hz =
				<75000000 300000000>,
				<0 0>,
				<0 0>,
				<75000000 300000000>,
				<75000000 300000000>,
				<0 0>,
				<0 0>,
				<0 0>;
			qcom,ice = <&ice>;

			status = "disabled";
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,sm8450-qmp-ufs-phy";
			reg = <0 0x01d87000 0 0x1000>;

			clock-names = "ref", "ref_aux", "qref";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
				 <&gcc GCC_UFS_0_CLKREF_EN>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";

			#clock-cells = <1>;
			#phy-cells = <0>;

			status = "disabled";
		};

		ice: crypto@1d88000 {
			compatible = "qcom,sm8450-inline-crypto-engine",
				     "qcom,inline-crypto-engine";
			reg = <0 0x01d88000 0 0x8000>;
			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
		};

		cryptobam: dma-controller@1dc4000 {
			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
			reg = <0 0x01dc4000 0 0x28000>;
			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			qcom,ee = <0>;
			qcom,controlled-remotely;
			iommus = <&apps_smmu 0x584 0x11>,
				 <&apps_smmu 0x588 0x0>,
				 <&apps_smmu 0x598 0x5>,
				 <&apps_smmu 0x59a 0x0>,
				 <&apps_smmu 0x59f 0x0>;
		};

		crypto: crypto@1dfa000 {
			compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
			reg = <0 0x01dfa000 0 0x6000>;
			dmas = <&cryptobam 4>, <&cryptobam 5>;
			dma-names = "rx", "tx";
			iommus = <&apps_smmu 0x584 0x11>,
				 <&apps_smmu 0x588 0x0>,
				 <&apps_smmu 0x598 0x5>,
				 <&apps_smmu 0x59a 0x0>,
				 <&apps_smmu 0x59f 0x0>;
			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
			interconnect-names = "memory";
		};

		sdhc_2: mmc@8804000 {
			compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x08804000 0 0x1000>;

			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface", "core", "xo";
			resets = <&gcc GCC_SDCC2_BCR>;
			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
			interconnect-names = "sdhc-ddr","cpu-sdhc";
			iommus = <&apps_smmu 0x4a0 0x0>;
			power-domains = <&rpmhpd RPMHPD_CX>;
			operating-points-v2 = <&sdhc2_opp_table>;
			bus-width = <4>;
			dma-coherent;

			/* Forbid SDR104/SDR50 - broken hw! */
			sdhci-caps-mask = <0x3 0x0>;

			status = "disabled";

			sdhc2_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};
			};
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
			reg = <0 0x0a6f8800 0 0x400>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB3_0_CLKREF_EN>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi",
				      "xo";

			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
			assigned-clock-rates = <19200000>, <200000000>;

			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
			interrupt-names = "hs_phy_irq",
					  "ss_phy_irq",
					  "dm_hs_phy_irq",
					  "dp_hs_phy_irq";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
			interconnect-names = "usb-ddr", "apps-usb";

			usb_1_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0 0x0a600000 0 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x0 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
				phy-names = "usb2-phy", "usb3-phy";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						usb_1_dwc3_hs: endpoint {
						};
					};

					port@1 {
						reg = <1>;

						usb_1_dwc3_ss: endpoint {
						};
					};
				};
			};
		};

		nsp_noc: interconnect@320c0000 {
			compatible = "qcom,sm8450-nsp-noc";
			reg = <0 0x320c0000 0 0x10000>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		lpass_ag_noc: interconnect@3c40000 {
			compatible = "qcom,sm8450-lpass-ag-noc";
			reg = <0 0x03c40000 0 0x17200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};
	};

	sound: sound {
	};

	thermal-zones {
		aoss0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 0>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpuss0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 1>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpuss1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 2>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpuss3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 3>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpuss4-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 4>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpu4-top-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 5>;

			trips {
				cpu4_top_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_top_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_top_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu4-bottom-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 6>;

			trips {
				cpu4_bottom_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_bottom_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu4_bottom_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu5-top-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 7>;

			trips {
				cpu5_top_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_top_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_top_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu5-bottom-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 8>;

			trips {
				cpu5_bottom_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_bottom_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu5_bottom_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu6-top-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 9>;

			trips {
				cpu6_top_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_top_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_top_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu6-bottom-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 10>;

			trips {
				cpu6_bottom_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_bottom_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu6_bottom_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu7-top-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 11>;

			trips {
				cpu7_top_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_top_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_top_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu7-middle-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 12>;

			trips {
				cpu7_middle_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_middle_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_middle_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu7-bottom-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 13>;

			trips {
				cpu7_bottom_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_bottom_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu7_bottom_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		gpu-top-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 14>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				thermal-hal-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};

				gpu0_tj_cfg: tj-cfg {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		gpu-bottom-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens0 15>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				thermal-hal-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};

				gpu1_tj_cfg: tj-cfg {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		aoss1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 0>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cpu0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 1>;

			trips {
				cpu0_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu0_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu0_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 2>;

			trips {
				cpu1_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu1_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu1_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu2-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 3>;

			trips {
				cpu2_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu2_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu2_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cpu3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 4>;

			trips {
				cpu3_alert0: trip-point0 {
					temperature = <90000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu3_alert1: trip-point1 {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu3_crit: cpu-crit {
					temperature = <110000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		cdsp0-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 5>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				thermal-hal-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};

				cdsp_0_config: junction-config {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cdsp1-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 6>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				thermal-hal-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};

				cdsp_1_config: junction-config {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		cdsp2-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 7>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				thermal-hal-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};

				cdsp_2_config: junction-config {
					temperature = <95000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		video-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 8>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		mem-thermal {
			polling-delay-passive = <10>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 9>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				ddr_config0: ddr0-config {
					temperature = <90000>;
					hysteresis = <5000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		modem0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 10>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				mdmss0_config0: mdmss0-config0 {
					temperature = <102000>;
					hysteresis = <3000>;
					type = "passive";
				};

				mdmss0_config1: mdmss0-config1 {
					temperature = <105000>;
					hysteresis = <3000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		modem1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 11>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				mdmss1_config0: mdmss1-config0 {
					temperature = <102000>;
					hysteresis = <3000>;
					type = "passive";
				};

				mdmss1_config1: mdmss1-config1 {
					temperature = <105000>;
					hysteresis = <3000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		modem2-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 12>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				mdmss2_config0: mdmss2-config0 {
					temperature = <102000>;
					hysteresis = <3000>;
					type = "passive";
				};

				mdmss2_config1: mdmss2-config1 {
					temperature = <105000>;
					hysteresis = <3000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		modem3-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 13>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				mdmss3_config0: mdmss3-config0 {
					temperature = <102000>;
					hysteresis = <3000>;
					type = "passive";
				};

				mdmss3_config1: mdmss3-config1 {
					temperature = <105000>;
					hysteresis = <3000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		camera0-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 14>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};

		camera1-thermal {
			polling-delay-passive = <0>;
			polling-delay = <0>;
			thermal-sensors = <&tsens1 15>;

			trips {
				thermal-engine-config {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "passive";
				};

				reset-mon-cfg {
					temperature = <115000>;
					hysteresis = <5000>;
					type = "passive";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};
};