2018-01-26 18:50:27 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2016-06-30 09:32:31 +00:00
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/*
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* Driver for the Aardvark PCIe controller, used on Marvell Armada
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* 3700.
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*
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* Copyright (C) 2016 Marvell
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*
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2016-08-01 17:32:13 +00:00
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* Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
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2016-06-30 09:32:31 +00:00
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*/
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#include <linux/delay.h>
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2020-09-07 11:10:34 +00:00
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#include <linux/gpio/consumer.h>
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2016-06-30 09:32:31 +00:00
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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2020-09-07 11:10:37 +00:00
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#include <linux/module.h>
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2016-06-30 09:32:31 +00:00
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#include <linux/pci.h>
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2020-11-29 23:07:39 +00:00
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#include <linux/pci-ecam.h>
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2016-08-01 17:32:13 +00:00
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#include <linux/init.h>
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2020-04-30 08:06:20 +00:00
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#include <linux/phy/phy.h>
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2016-06-30 09:32:31 +00:00
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#include <linux/platform_device.h>
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2019-09-03 11:30:59 +00:00
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#include <linux/msi.h>
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2016-06-30 09:32:31 +00:00
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#include <linux/of_address.h>
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2020-04-30 08:06:18 +00:00
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#include <linux/of_gpio.h>
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2016-06-30 09:32:31 +00:00
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#include <linux/of_pci.h>
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2018-05-11 17:15:30 +00:00
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#include "../pci.h"
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2018-10-18 15:37:19 +00:00
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#include "../pci-bridge-emul.h"
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2018-05-11 17:15:30 +00:00
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2016-06-30 09:32:31 +00:00
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/* PCIe core registers */
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2018-10-18 15:37:19 +00:00
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#define PCIE_CORE_DEV_ID_REG 0x0
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2016-06-30 09:32:31 +00:00
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#define PCIE_CORE_CMD_STATUS_REG 0x4
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2018-10-18 15:37:19 +00:00
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#define PCIE_CORE_DEV_REV_REG 0x8
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#define PCIE_CORE_PCIEXP_CAP 0xc0
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2016-06-30 09:32:31 +00:00
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#define PCIE_CORE_ERR_CAPCTL_REG 0x118
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
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#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
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/* PIO registers base address and register offsets */
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#define PIO_BASE_ADDR 0x4000
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#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
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#define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
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#define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
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#define PIO_STAT (PIO_BASE_ADDR + 0x4)
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#define PIO_COMPLETION_STATUS_SHIFT 7
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#define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
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#define PIO_COMPLETION_STATUS_OK 0
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#define PIO_COMPLETION_STATUS_UR 1
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#define PIO_COMPLETION_STATUS_CRS 2
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#define PIO_COMPLETION_STATUS_CA 4
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2021-06-24 21:33:43 +00:00
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#define PIO_NON_POSTED_REQ BIT(10)
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2021-07-22 14:40:38 +00:00
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#define PIO_ERR_STATUS BIT(11)
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2016-06-30 09:32:31 +00:00
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#define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
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#define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
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#define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
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#define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
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#define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
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#define PIO_START (PIO_BASE_ADDR + 0x1c)
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#define PIO_ISR (PIO_BASE_ADDR + 0x20)
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#define PIO_ISRM (PIO_BASE_ADDR + 0x24)
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/* Aardvark Control registers */
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#define CONTROL_BASE_ADDR 0x4800
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#define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
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#define PCIE_GEN_SEL_MSK 0x3
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#define PCIE_GEN_SEL_SHIFT 0x0
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#define SPEED_GEN_1 0
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#define SPEED_GEN_2 1
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#define SPEED_GEN_3 2
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#define IS_RC_MSK 1
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#define IS_RC_SHIFT 2
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#define LANE_CNT_MSK 0x18
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#define LANE_CNT_SHIFT 0x3
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#define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
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#define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
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#define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
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#define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
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#define LINK_TRAINING_EN BIT(6)
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#define LEGACY_INTA BIT(28)
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#define LEGACY_INTB BIT(29)
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#define LEGACY_INTC BIT(30)
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#define LEGACY_INTD BIT(31)
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#define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
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#define HOT_RESET_GEN BIT(0)
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#define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
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#define PCIE_CORE_CTRL2_RESERVED 0x7
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#define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
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#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
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#define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
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#define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
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2020-04-30 08:06:20 +00:00
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#define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
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#define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
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2021-10-05 18:09:44 +00:00
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#define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
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2018-10-18 15:37:19 +00:00
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#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
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2016-06-30 09:32:31 +00:00
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#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
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2018-10-18 15:37:19 +00:00
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#define PCIE_MSG_PM_PME_MASK BIT(7)
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2016-06-30 09:32:31 +00:00
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#define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
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#define PCIE_ISR0_MSI_INT_PENDING BIT(24)
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2022-01-10 01:50:08 +00:00
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#define PCIE_ISR0_CORR_ERR BIT(11)
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#define PCIE_ISR0_NFAT_ERR BIT(12)
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#define PCIE_ISR0_FAT_ERR BIT(13)
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#define PCIE_ISR0_ERR_MASK GENMASK(13, 11)
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2016-06-30 09:32:31 +00:00
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#define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
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#define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
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2021-10-05 18:09:46 +00:00
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#define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
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2016-06-30 09:32:31 +00:00
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#define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
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#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
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#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
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#define PCIE_ISR1_FLUSH BIT(5)
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2018-04-06 14:55:33 +00:00
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#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
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2021-10-05 18:09:46 +00:00
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#define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
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2016-06-30 09:32:31 +00:00
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#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
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#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
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#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
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#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
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2021-11-30 17:29:06 +00:00
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#define PCIE_MSI_ALL_MASK GENMASK(31, 0)
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2016-06-30 09:32:31 +00:00
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#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
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2021-10-28 18:56:55 +00:00
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#define PCIE_MSI_DATA_MASK GENMASK(15, 0)
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2016-06-30 09:32:31 +00:00
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2021-06-24 21:55:45 +00:00
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/* PCIe window configuration */
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#define OB_WIN_BASE_ADDR 0x4c00
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#define OB_WIN_BLOCK_SIZE 0x20
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#define OB_WIN_COUNT 8
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#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
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OB_WIN_BLOCK_SIZE * (win) + \
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(offset))
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#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
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#define OB_WIN_ENABLE BIT(0)
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#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
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#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
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#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
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#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
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#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
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#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
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#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
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#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
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#define OB_WIN_FUNC_NUM_SHIFT 24
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#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
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#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
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#define OB_WIN_BUS_NUM_BITS_SHIFT 20
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#define OB_WIN_MSG_CODE_ENABLE BIT(22)
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#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
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#define OB_WIN_MSG_CODE_SHIFT 14
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#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
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#define OB_WIN_ATTR_ENABLE BIT(11)
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#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
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#define OB_WIN_ATTR_TC_SHIFT 8
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#define OB_WIN_ATTR_RELAXED BIT(7)
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#define OB_WIN_ATTR_NOSNOOP BIT(6)
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#define OB_WIN_ATTR_POISON BIT(5)
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#define OB_WIN_ATTR_IDO BIT(4)
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#define OB_WIN_TYPE_MASK GENMASK(3, 0)
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#define OB_WIN_TYPE_SHIFT 0
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#define OB_WIN_TYPE_MEM 0x0
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#define OB_WIN_TYPE_IO 0x4
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#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
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#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
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#define OB_WIN_TYPE_MSG 0xc
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2016-06-30 09:32:31 +00:00
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/* LMI registers base address and register offsets */
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#define LMI_BASE_ADDR 0x6000
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#define CFG_REG (LMI_BASE_ADDR + 0x0)
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#define LTSSM_SHIFT 24
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#define LTSSM_MASK 0x3f
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#define RC_BAR_CONFIG 0x300
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2021-10-05 18:09:51 +00:00
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/* LTSSM values in CFG_REG */
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enum {
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LTSSM_DETECT_QUIET = 0x0,
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LTSSM_DETECT_ACTIVE = 0x1,
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LTSSM_POLLING_ACTIVE = 0x2,
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LTSSM_POLLING_COMPLIANCE = 0x3,
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LTSSM_POLLING_CONFIGURATION = 0x4,
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LTSSM_CONFIG_LINKWIDTH_START = 0x5,
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LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
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LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
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LTSSM_CONFIG_LANENUM_WAIT = 0x8,
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LTSSM_CONFIG_COMPLETE = 0x9,
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LTSSM_CONFIG_IDLE = 0xa,
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LTSSM_RECOVERY_RCVR_LOCK = 0xb,
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LTSSM_RECOVERY_SPEED = 0xc,
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LTSSM_RECOVERY_RCVR_CFG = 0xd,
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LTSSM_RECOVERY_IDLE = 0xe,
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LTSSM_L0 = 0x10,
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LTSSM_RX_L0S_ENTRY = 0x11,
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LTSSM_RX_L0S_IDLE = 0x12,
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LTSSM_RX_L0S_FTS = 0x13,
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LTSSM_TX_L0S_ENTRY = 0x14,
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LTSSM_TX_L0S_IDLE = 0x15,
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LTSSM_TX_L0S_FTS = 0x16,
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LTSSM_L1_ENTRY = 0x17,
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LTSSM_L1_IDLE = 0x18,
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LTSSM_L2_IDLE = 0x19,
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LTSSM_L2_TRANSMIT_WAKE = 0x1a,
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LTSSM_DISABLED = 0x20,
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LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
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LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
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LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
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LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
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LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
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LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
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LTSSM_HOT_RESET = 0x27,
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LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
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LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
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LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
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LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
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};
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2021-06-24 22:26:20 +00:00
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#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
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2016-06-30 09:32:31 +00:00
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/* PCIe core controller registers */
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#define CTRL_CORE_BASE_ADDR 0x18000
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#define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
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#define CTRL_MODE_SHIFT 0x0
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#define CTRL_MODE_MASK 0x1
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#define PCIE_CORE_MODE_DIRECT 0x0
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#define PCIE_CORE_MODE_COMMAND 0x1
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/* PCIe Central Interrupts Registers */
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#define CENTRAL_INT_BASE_ADDR 0x1b000
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#define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
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#define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
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#define PCIE_IRQ_CMDQ_INT BIT(0)
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#define PCIE_IRQ_MSI_STATUS_INT BIT(1)
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#define PCIE_IRQ_CMD_SENT_DONE BIT(3)
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#define PCIE_IRQ_DMA_INT BIT(4)
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#define PCIE_IRQ_IB_DXFERDONE BIT(5)
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#define PCIE_IRQ_OB_DXFERDONE BIT(6)
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#define PCIE_IRQ_OB_RXFERDONE BIT(7)
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#define PCIE_IRQ_COMPQ_INT BIT(12)
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#define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
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#define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
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#define PCIE_IRQ_CORE_INT BIT(16)
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#define PCIE_IRQ_CORE_INT_PIO BIT(17)
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#define PCIE_IRQ_DPMU_INT BIT(18)
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#define PCIE_IRQ_PCIE_MIS_INT BIT(19)
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#define PCIE_IRQ_MSI_INT1_DET BIT(20)
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#define PCIE_IRQ_MSI_INT2_DET BIT(21)
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#define PCIE_IRQ_RC_DBELL_DET BIT(22)
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#define PCIE_IRQ_EP_STATUS BIT(23)
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2021-10-05 18:09:46 +00:00
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#define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
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2016-06-30 09:32:31 +00:00
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#define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
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/* Transaction types */
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#define PCIE_CONFIG_RD_TYPE0 0x8
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#define PCIE_CONFIG_RD_TYPE1 0x9
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#define PCIE_CONFIG_WR_TYPE0 0xa
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#define PCIE_CONFIG_WR_TYPE1 0xb
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2021-07-22 14:40:39 +00:00
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#define PIO_RETRY_CNT 750000 /* 1.5 s */
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2019-09-27 08:55:02 +00:00
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#define PIO_RETRY_DELAY 2 /* 2 us*/
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2016-06-30 09:32:31 +00:00
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
|
|
|
|
#define LINK_WAIT_USLEEP_MAX 100000
|
2019-05-22 21:33:51 +00:00
|
|
|
#define RETRAIN_WAIT_MAX_RETRIES 10
|
|
|
|
#define RETRAIN_WAIT_USLEEP_US 2000
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
#define MSI_IRQ_NUM 32
|
|
|
|
|
2021-07-22 14:40:41 +00:00
|
|
|
#define CFG_RD_CRS_VAL 0xffff0001
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
struct advk_pcie {
|
|
|
|
struct platform_device *pdev;
|
|
|
|
void __iomem *base;
|
2021-06-24 21:55:45 +00:00
|
|
|
struct {
|
|
|
|
phys_addr_t match;
|
|
|
|
phys_addr_t remap;
|
|
|
|
phys_addr_t mask;
|
|
|
|
u32 actions;
|
|
|
|
} wins[OB_WIN_COUNT];
|
|
|
|
u8 wins_count;
|
2022-01-10 01:49:59 +00:00
|
|
|
int irq;
|
2022-01-10 01:50:13 +00:00
|
|
|
struct irq_domain *rp_irq_domain;
|
2016-06-30 09:32:31 +00:00
|
|
|
struct irq_domain *irq_domain;
|
|
|
|
struct irq_chip irq_chip;
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spinlock_t irq_lock;
|
2016-06-30 09:32:31 +00:00
|
|
|
struct irq_domain *msi_domain;
|
2017-02-28 14:31:14 +00:00
|
|
|
struct irq_domain *msi_inner_domain;
|
2022-01-10 01:50:05 +00:00
|
|
|
raw_spinlock_t msi_irq_lock;
|
2017-02-28 14:31:14 +00:00
|
|
|
DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
|
2016-06-30 09:32:31 +00:00
|
|
|
struct mutex msi_used_lock;
|
2020-04-30 08:06:17 +00:00
|
|
|
int link_gen;
|
2018-10-18 15:37:19 +00:00
|
|
|
struct pci_bridge_emul bridge;
|
2020-04-30 08:06:18 +00:00
|
|
|
struct gpio_desc *reset_gpio;
|
2020-04-30 08:06:20 +00:00
|
|
|
struct phy *phy;
|
2016-06-30 09:32:31 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
|
|
|
|
{
|
|
|
|
writel(val, pcie->base + reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
|
|
|
|
{
|
|
|
|
return readl(pcie->base + reg);
|
|
|
|
}
|
|
|
|
|
2021-10-05 18:09:51 +00:00
|
|
|
static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2021-10-05 18:09:51 +00:00
|
|
|
u32 val;
|
|
|
|
u8 ltssm_state;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
val = advk_readl(pcie, CFG_REG);
|
|
|
|
ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
|
2021-10-05 18:09:51 +00:00
|
|
|
return ltssm_state;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
/* check if LTSSM is in normal operation - some L* state */
|
|
|
|
u8 ltssm_state = advk_pcie_ltssm_state(pcie);
|
|
|
|
return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
|
|
|
|
}
|
|
|
|
|
2021-10-05 18:09:52 +00:00
|
|
|
static inline bool advk_pcie_link_active(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* According to PCIe Base specification 3.0, Table 4-14: Link
|
|
|
|
* Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle
|
|
|
|
* is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0,
|
|
|
|
* L0s, L1 and L2 states. And according to 3.2.1. Data Link
|
|
|
|
* Control and Management State Machine Rules is DL Up status
|
|
|
|
* reported in DL Active state.
|
|
|
|
*/
|
|
|
|
u8 ltssm_state = advk_pcie_ltssm_state(pcie);
|
|
|
|
return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED;
|
|
|
|
}
|
|
|
|
|
2021-10-05 18:09:51 +00:00
|
|
|
static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* According to PCIe Base specification 3.0, Table 4-14: Link
|
|
|
|
* Status Mapped to the LTSSM is Link Training mapped to LTSSM
|
|
|
|
* Configuration and Recovery states.
|
|
|
|
*/
|
|
|
|
u8 ltssm_state = advk_pcie_ltssm_state(pcie);
|
|
|
|
return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START &&
|
|
|
|
ltssm_state < LTSSM_L0) ||
|
|
|
|
(ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 &&
|
|
|
|
ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3));
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
int retries;
|
|
|
|
|
|
|
|
/* check if the link is up or not */
|
|
|
|
for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
|
2020-04-30 08:06:17 +00:00
|
|
|
if (advk_pcie_link_up(pcie))
|
2016-06-30 09:32:31 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2019-05-22 21:33:51 +00:00
|
|
|
static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
size_t retries;
|
|
|
|
|
|
|
|
for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
|
2021-10-05 18:09:51 +00:00
|
|
|
if (advk_pcie_link_training(pcie))
|
2019-05-22 21:33:51 +00:00
|
|
|
break;
|
|
|
|
udelay(RETRAIN_WAIT_USLEEP_US);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-07 11:10:38 +00:00
|
|
|
static void advk_pcie_issue_perst(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
if (!pcie->reset_gpio)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* 10ms delay is needed for some cards */
|
|
|
|
dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
|
|
|
|
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
|
|
|
|
usleep_range(10000, 11000);
|
|
|
|
gpiod_set_value_cansleep(pcie->reset_gpio, 0);
|
|
|
|
}
|
|
|
|
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
static void advk_pcie_train_link(struct advk_pcie *pcie)
|
2020-04-30 08:06:17 +00:00
|
|
|
{
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
struct device *dev = &pcie->pdev->dev;
|
2020-04-30 08:06:17 +00:00
|
|
|
u32 reg;
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
int ret;
|
2020-04-30 08:06:17 +00:00
|
|
|
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
/*
|
|
|
|
* Setup PCIe rev / gen compliance based on device tree property
|
|
|
|
* 'max-link-speed' which also forces maximal link speed.
|
|
|
|
*/
|
2020-04-30 08:06:17 +00:00
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
|
reg &= ~PCIE_GEN_SEL_MSK;
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
if (pcie->link_gen == 3)
|
2020-04-30 08:06:17 +00:00
|
|
|
reg |= SPEED_GEN_3;
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
else if (pcie->link_gen == 2)
|
2020-04-30 08:06:17 +00:00
|
|
|
reg |= SPEED_GEN_2;
|
|
|
|
else
|
|
|
|
reg |= SPEED_GEN_1;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
|
|
|
|
|
/*
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
* Set maximal link speed value also into PCIe Link Control 2 register.
|
|
|
|
* Armada 3700 Functional Specification says that default value is based
|
|
|
|
* on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
|
2020-04-30 08:06:17 +00:00
|
|
|
*/
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
|
|
|
|
reg &= ~PCI_EXP_LNKCTL2_TLS;
|
|
|
|
if (pcie->link_gen == 3)
|
|
|
|
reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
|
|
|
|
else if (pcie->link_gen == 2)
|
|
|
|
reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
|
|
|
|
else
|
|
|
|
reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
|
|
|
|
|
|
|
|
/* Enable link training after selecting PCIe generation */
|
2020-04-30 08:06:17 +00:00
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
|
reg |= LINK_TRAINING_EN;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
|
|
2020-09-07 11:10:38 +00:00
|
|
|
/*
|
|
|
|
* Reset PCIe card via PERST# signal. Some cards are not detected
|
|
|
|
* during link training when they are in some non-initial state.
|
|
|
|
*/
|
|
|
|
advk_pcie_issue_perst(pcie);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PERST# signal could have been asserted by pinctrl subsystem before
|
|
|
|
* probe() callback has been called or issued explicitly by reset gpio
|
|
|
|
* function advk_pcie_issue_perst(), making the endpoint going into
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
* fundamental reset. As required by PCI Express spec (PCI Express
|
|
|
|
* Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1
|
|
|
|
* Conventional Reset) a delay for at least 100ms after such a reset
|
|
|
|
* before sending a Configuration Request to the device is needed.
|
|
|
|
* So wait until PCIe link is up. Function advk_pcie_wait_for_link()
|
|
|
|
* waits for link at least 900ms.
|
2020-04-30 08:06:17 +00:00
|
|
|
*/
|
PCI: aardvark: Fix link training
Fix multiple link training issues in aardvark driver. The main reason of
these issues was misunderstanding of what certain registers do, since their
names and comments were misleading: before commit 96be36dbffac ("PCI:
aardvark: Replace custom macros by standard linux/pci_regs.h macros"), the
pci-aardvark.c driver used custom macros for accessing standard PCIe Root
Bridge registers, and misleading comments did not help to understand what
the code was really doing.
After doing more tests and experiments I've come to the conclusion that the
SPEED_GEN register in aardvark sets the PCIe revision / generation
compliance and forces maximal link speed. Both GEN3 and GEN2 values set the
read-only PCI_EXP_FLAGS_VERS bits (PCIe capabilities version of Root
Bridge) to value 2, while GEN1 value sets PCI_EXP_FLAGS_VERS to 1, which
matches with PCI Express specifications revisions 3, 2 and 1 respectively.
Changing SPEED_GEN also sets the read-only bits PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKCAP2_SLS to corresponding speed.
(Note that PCI Express rev 1 specification does not define PCI_EXP_LNKCAP2
and PCI_EXP_LNKCTL2 registers and when SPEED_GEN is set to GEN1 (which
also sets PCI_EXP_FLAGS_VERS set to 1), lspci cannot access
PCI_EXP_LNKCAP2 and PCI_EXP_LNKCTL2 registers.)
Changing PCIe link speed can be done via PCI_EXP_LNKCTL2_TLS bits of
PCI_EXP_LNKCTL2 register. Armada 3700 Functional Specifications says that
the default value of PCI_EXP_LNKCTL2_TLS is based on SPEED_GEN value, but
tests showed that the default value is always 8.0 GT/s, independently of
speed set by SPEED_GEN. So after setting SPEED_GEN, we must also set value
in PCI_EXP_LNKCTL2 register via PCI_EXP_LNKCTL2_TLS bits.
Triggering PCI_EXP_LNKCTL_RL bit immediately after setting LINK_TRAINING_EN
bit actually doesn't do anything. Tests have shown that a delay is needed
after enabling LINK_TRAINING_EN bit. As triggering PCI_EXP_LNKCTL_RL
currently does nothing, remove it.
Commit 43fc679ced18 ("PCI: aardvark: Improve link training") introduced
code which sets SPEED_GEN register based on negotiated link speed from
PCI_EXP_LNKSTA_CLS bits of PCI_EXP_LNKSTA register. This code was added to
fix detection of Compex WLE900VX (Atheros QCA9880) WiFi GEN1 PCIe cards, as
otherwise these cards were "invisible" on PCIe bus (probably because they
crashed). But apparently more people reported the same issues with these
cards also with other PCIe controllers [1] and I was able to reproduce this
issue also with other "noname" WiFi cards based on Atheros QCA9890 chip
(with the same PCI vendor/device ids as Atheros QCA9880). So this is not an
issue in aardvark but rather an issue in Atheros QCA98xx chips. Also, this
issue only exists if the kernel is compiled with PCIe ASPM support, and a
generic workaround for this is to change PCIe Bridge to 2.5 GT/s link speed
via PCI_EXP_LNKCTL2_TLS_2_5GT bits in PCI_EXP_LNKCTL2 register [2], before
triggering PCI_EXP_LNKCTL_RL bit. This workaround also works when SPEED_GEN
is set to value GEN2 (5 GT/s). So remove this hack completely in the
aardvark driver and always set SPEED_GEN to value from 'max-link-speed' DT
property. Fix for Atheros QCA98xx chips is handled separately by patch [2].
These two things (code for triggering PCI_EXP_LNKCTL_RL bit and changing
SPEED_GEN value) also explain why commit 6964494582f5 ("PCI: aardvark:
Train link immediately after enabling training") somehow fixed detection of
those problematic Compex cards with Atheros chips: if triggering link
retraining (via PCI_EXP_LNKCTL_RL bit) was done immediately after enabling
link training (via LINK_TRAINING_EN), it did nothing. If there was a
specific delay, aardvark HW already initialized PCIe link and therefore
triggering link retraining caused the above issue. Compex cards triggered
link down event and disappeared from the PCIe bus.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready before
training link") added 100ms sleep before calling 'Start link training'
command and explained that it is a requirement of PCI Express
specification. But the code after this 100ms sleep was not doing 'Start
link training', rather it triggered PCI_EXP_LNKCTL_RL bit via PCIe Root
Bridge to put link into Recovery state.
The required delay after fundamental reset is already done in function
advk_pcie_wait_for_link() which also checks whether PCIe link is up.
So after removing the code which triggers PCI_EXP_LNKCTL_RL bit on PCIe
Root Bridge, there is no need to wait 100ms again. Remove the extra
msleep() call and update comment about the delay required by the PCI
Express specification.
According to Marvell Armada 3700 Functional Specifications, Link training
should be enabled via aardvark register LINK_TRAINING_EN after selecting
PCIe generation and x1 lane. There is no need to disable it prior resetting
card via PERST# signal. This disabling code was introduced in commit
5169a9851daa ("PCI: aardvark: Issue PERST via GPIO") as a workaround for
some Atheros cards. It turns out that this also is Atheros specific issue
and affects any PCIe controller, not only aardvark. Moreover this Atheros
issue was triggered by juggling with PCI_EXP_LNKCTL_RL, LINK_TRAINING_EN
and SPEED_GEN bits interleaved with sleeps. Now, after removing triggering
PCI_EXP_LNKCTL_RL, there is no need to explicitly disable LINK_TRAINING_EN
bit. So remove this code too. The problematic Compex cards described in
previous git commits are correctly detected in advk_pcie_train_link()
function even after applying all these changes.
Note that with this patch, and also prior this patch, some NVMe disks which
support PCIe GEN3 with 8 GT/s speed are negotiated only at the lowest link
speed 2.5 GT/s, independently of SPEED_GEN value. After manually triggering
PCI_EXP_LNKCTL_RL bit (e.g. from userspace via setpci), these NVMe disks
change link speed to 5 GT/s when SPEED_GEN was configured to GEN2. This
issue first needs to be properly investigated. I will send a fix in the
future.
On the other hand, some other GEN2 PCIe cards with 5 GT/s speed are
autonomously by HW autonegotiated at full 5 GT/s speed without need of any
software interaction.
Armada 3700 Functional Specifications describes the following steps for
link training: set SPEED_GEN to GEN2, enable LINK_TRAINING_EN, poll until
link training is complete, trigger PCI_EXP_LNKCTL_RL, poll until signal
rate is 5 GT/s, poll until link training is complete, enable ASPM L0s.
The requirement for triggering PCI_EXP_LNKCTL_RL can be explained by the
need to achieve 5 GT/s speed (as changing link speed is done by throw to
recovery state entered by PCI_EXP_LNKCTL_RL) or maybe as a part of enabling
ASPM L0s (but in this case ASPM L0s should have been enabled prior
PCI_EXP_LNKCTL_RL).
It is unknown why the original pci-aardvark.c driver was triggering
PCI_EXP_LNKCTL_RL bit before waiting for the link to be up. This does not
align with neither PCIe base specifications nor with Armada 3700 Functional
Specification. (Note that in older versions of aardvark, this bit was
called incorrectly PCIE_CORE_LINK_TRAINING, so this may be the reason.)
It is also unknown why Armada 3700 Functional Specification says that it is
needed to trigger PCI_EXP_LNKCTL_RL for GEN2 mode, as according to PCIe
base specification 5 GT/s speed negotiation is supposed to be entirely
autonomous, even if initial speed is 2.5 GT/s.
[1] - https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
[2] - https://lore.kernel.org/linux-pci/20210326124326.21163-1-pali@kernel.org/
Link: https://lore.kernel.org/r/20211005180952.6812-12-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
2021-10-05 18:09:50 +00:00
|
|
|
ret = advk_pcie_wait_for_link(pcie);
|
|
|
|
if (ret < 0)
|
|
|
|
dev_err(dev, "link never came up\n");
|
|
|
|
else
|
|
|
|
dev_info(dev, "link up\n");
|
2020-04-30 08:06:17 +00:00
|
|
|
}
|
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
/*
|
|
|
|
* Set PCIe address window register which could be used for memory
|
|
|
|
* mapping.
|
|
|
|
*/
|
|
|
|
static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
|
|
|
|
phys_addr_t match, phys_addr_t remap,
|
|
|
|
phys_addr_t mask, u32 actions)
|
|
|
|
{
|
|
|
|
advk_writel(pcie, OB_WIN_ENABLE |
|
|
|
|
lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
|
|
|
|
advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
|
|
|
|
advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
|
|
|
|
advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
|
|
|
|
advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
|
|
|
|
advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
|
|
|
|
advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
|
|
|
|
{
|
|
|
|
advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
|
|
|
|
advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
|
|
|
{
|
2022-01-10 01:50:06 +00:00
|
|
|
phys_addr_t msi_addr;
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 reg;
|
2021-06-24 21:55:45 +00:00
|
|
|
int i;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:44 +00:00
|
|
|
/*
|
|
|
|
* Configure PCIe Reference clock. Direction is from the PCIe
|
|
|
|
* controller to the endpoint card, so enable transmitting of
|
|
|
|
* Reference clock differential signal off-chip and disable
|
|
|
|
* receiving off-chip differential signal.
|
|
|
|
*/
|
2020-04-30 08:06:20 +00:00
|
|
|
reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
|
|
|
|
reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
|
2021-10-05 18:09:44 +00:00
|
|
|
reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE;
|
2020-04-30 08:06:20 +00:00
|
|
|
advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
/* Set to Direct mode */
|
|
|
|
reg = advk_readl(pcie, CTRL_CONFIG_REG);
|
|
|
|
reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
|
|
|
|
reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
|
|
|
|
advk_writel(pcie, reg, CTRL_CONFIG_REG);
|
|
|
|
|
|
|
|
/* Set PCI global control register to RC mode */
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
|
reg |= (IS_RC_MSK << IS_RC_SHIFT);
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
|
|
2021-06-24 22:26:20 +00:00
|
|
|
/*
|
|
|
|
* Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
|
|
|
|
* VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
|
|
|
|
* id in high 16 bits. Updating this register changes readback value of
|
|
|
|
* read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
|
|
|
|
* for erratum 4.1: "The value of device and vendor ID is incorrect".
|
|
|
|
*/
|
|
|
|
reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
|
|
|
|
advk_writel(pcie, reg, VENDOR_ID_REG);
|
|
|
|
|
2021-10-28 18:56:57 +00:00
|
|
|
/*
|
|
|
|
* Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
|
|
|
|
* because the default value is Mass storage controller (0x010400).
|
|
|
|
*
|
|
|
|
* Note that this Aardvark PCI Bridge does not have compliant Type 1
|
|
|
|
* Configuration Space and it even cannot be accessed via Aardvark's
|
|
|
|
* PCI config space access method. Something like config space is
|
|
|
|
* available in internal Aardvark registers starting at offset 0x0
|
|
|
|
* and is reported as Type 0. In range 0x10 - 0x34 it has totally
|
|
|
|
* different registers.
|
|
|
|
*
|
|
|
|
* Therefore driver uses emulation of PCI Bridge which emulates
|
|
|
|
* access to configuration space via internal Aardvark registers or
|
|
|
|
* emulated configuration buffer.
|
|
|
|
*/
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
|
|
|
|
reg &= ~0xffffff00;
|
|
|
|
reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
|
|
|
|
|
2021-10-28 18:56:56 +00:00
|
|
|
/* Disable Root Bridge I/O space, memory space and bus mastering */
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
/* Set Advanced Error Capabilities and Control PF0 register */
|
|
|
|
reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
|
|
|
|
PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
|
|
|
|
PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
|
|
|
|
PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
|
|
|
|
|
2020-04-30 08:06:21 +00:00
|
|
|
/* Set PCIe Device Control register */
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
|
|
|
|
reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
|
|
|
|
reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
|
2021-10-05 18:09:41 +00:00
|
|
|
reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
2020-04-30 08:06:21 +00:00
|
|
|
reg &= ~PCI_EXP_DEVCTL_READRQ;
|
2021-10-05 18:09:41 +00:00
|
|
|
reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
|
2020-04-30 08:06:21 +00:00
|
|
|
reg |= PCI_EXP_DEVCTL_READRQ_512B;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
/* Program PCIe Control 2 to disable strict ordering */
|
|
|
|
reg = PCIE_CORE_CTRL2_RESERVED |
|
|
|
|
PCIE_CORE_CTRL2_TD_ENABLE;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
|
|
|
|
|
/* Set lane X1 */
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
|
reg &= ~LANE_CNT_MSK;
|
|
|
|
reg |= LANE_COUNT_1;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
|
|
|
2022-01-10 01:50:06 +00:00
|
|
|
/* Set MSI address */
|
|
|
|
msi_addr = virt_to_phys(pcie);
|
|
|
|
advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);
|
|
|
|
advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
/* Enable MSI */
|
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
|
|
|
|
reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
|
|
|
|
|
/* Clear all interrupts */
|
2021-11-30 17:29:06 +00:00
|
|
|
advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
|
|
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
|
|
|
|
advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
|
|
|
|
|
2022-01-10 01:50:05 +00:00
|
|
|
/* Disable All ISR0/1 and MSI Sources */
|
2022-01-10 01:50:04 +00:00
|
|
|
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
|
2022-01-10 01:50:05 +00:00
|
|
|
advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:50:04 +00:00
|
|
|
/* Unmask summary MSI interrupt */
|
|
|
|
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
|
|
|
reg &= ~PCIE_ISR0_MSI_INT_PENDING;
|
|
|
|
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
|
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
/* Unmask PME interrupt for processing of PME requester */
|
|
|
|
reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
|
|
|
reg &= ~PCIE_MSG_PM_PME_MASK;
|
|
|
|
advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
/* Enable summary interrupt for GIC SPI source */
|
|
|
|
reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
|
|
|
|
advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
|
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
/*
|
|
|
|
* Enable AXI address window location generation:
|
|
|
|
* When it is enabled, the default outbound window
|
|
|
|
* configurations (Default User Field: 0xD0074CFC)
|
|
|
|
* are used to transparent address translation for
|
|
|
|
* the outbound transactions. Thus, PCIe address
|
|
|
|
* windows are not required for transparent memory
|
|
|
|
* access when default outbound window configuration
|
|
|
|
* is set for memory access.
|
|
|
|
*/
|
2016-06-30 09:32:31 +00:00
|
|
|
reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
|
|
|
|
reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
|
|
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
/*
|
|
|
|
* Set memory access in Default User Field so it
|
|
|
|
* is not required to configure PCIe address for
|
|
|
|
* transparent memory access.
|
|
|
|
*/
|
|
|
|
advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Bypass the address window mapping for PIO:
|
|
|
|
* Since PIO access already contains all required
|
|
|
|
* info over AXI interface by PIO registers, the
|
|
|
|
* address window is not required.
|
|
|
|
*/
|
2016-06-30 09:32:31 +00:00
|
|
|
reg = advk_readl(pcie, PIO_CTRL);
|
|
|
|
reg |= PIO_CTRL_ADDR_WIN_DISABLE;
|
|
|
|
advk_writel(pcie, reg, PIO_CTRL);
|
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
/*
|
|
|
|
* Configure PCIe address windows for non-memory or
|
|
|
|
* non-transparent access as by default PCIe uses
|
|
|
|
* transparent memory access.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < pcie->wins_count; i++)
|
|
|
|
advk_pcie_set_ob_win(pcie, i,
|
|
|
|
pcie->wins[i].match, pcie->wins[i].remap,
|
|
|
|
pcie->wins[i].mask, pcie->wins[i].actions);
|
|
|
|
|
|
|
|
/* Disable remaining PCIe outbound windows */
|
|
|
|
for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
|
|
|
|
advk_pcie_disable_ob_win(pcie, i);
|
|
|
|
|
2020-04-30 08:06:17 +00:00
|
|
|
advk_pcie_train_link(pcie);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2021-07-22 14:40:41 +00:00
|
|
|
static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2016-10-06 18:27:46 +00:00
|
|
|
struct device *dev = &pcie->pdev->dev;
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 reg;
|
|
|
|
unsigned int status;
|
|
|
|
char *strcomp_status, *str_posted;
|
2021-10-05 18:09:48 +00:00
|
|
|
int ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
reg = advk_readl(pcie, PIO_STAT);
|
|
|
|
status = (reg & PIO_COMPLETION_STATUS_MASK) >>
|
|
|
|
PIO_COMPLETION_STATUS_SHIFT;
|
|
|
|
|
2021-07-22 14:40:38 +00:00
|
|
|
/*
|
|
|
|
* According to HW spec, the PIO status check sequence as below:
|
|
|
|
* 1) even if COMPLETION_STATUS(bit9:7) indicates successful,
|
|
|
|
* it still needs to check Error Status(bit11), only when this bit
|
|
|
|
* indicates no error happen, the operation is successful.
|
|
|
|
* 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
|
|
|
|
* means a PIO write error, and for PIO read it is successful with
|
|
|
|
* a read value of 0xFFFFFFFF.
|
|
|
|
* 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
|
|
|
|
* only means a PIO write error, and for PIO read it is successful
|
|
|
|
* with a read value of 0xFFFF0001.
|
|
|
|
* 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
|
|
|
|
* error for both PIO read and PIO write operation.
|
|
|
|
* 5) other errors are indicated as 'unknown'.
|
|
|
|
*/
|
2016-06-30 09:32:31 +00:00
|
|
|
switch (status) {
|
2021-07-22 14:40:38 +00:00
|
|
|
case PIO_COMPLETION_STATUS_OK:
|
|
|
|
if (reg & PIO_ERR_STATUS) {
|
|
|
|
strcomp_status = "COMP_ERR";
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = -EFAULT;
|
2021-07-22 14:40:38 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Get the read result */
|
|
|
|
if (val)
|
|
|
|
*val = advk_readl(pcie, PIO_RD_DATA);
|
|
|
|
/* No error */
|
|
|
|
strcomp_status = NULL;
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = 0;
|
2021-07-22 14:40:38 +00:00
|
|
|
break;
|
2016-06-30 09:32:31 +00:00
|
|
|
case PIO_COMPLETION_STATUS_UR:
|
|
|
|
strcomp_status = "UR";
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = -EOPNOTSUPP;
|
2016-06-30 09:32:31 +00:00
|
|
|
break;
|
|
|
|
case PIO_COMPLETION_STATUS_CRS:
|
2021-07-22 14:40:41 +00:00
|
|
|
if (allow_crs && val) {
|
|
|
|
/* PCIe r4.0, sec 2.3.2, says:
|
|
|
|
* If CRS Software Visibility is enabled:
|
|
|
|
* For a Configuration Read Request that includes both
|
|
|
|
* bytes of the Vendor ID field of a device Function's
|
|
|
|
* Configuration Space Header, the Root Complex must
|
|
|
|
* complete the Request to the host by returning a
|
|
|
|
* read-data value of 0001h for the Vendor ID field and
|
|
|
|
* all '1's for any additional bytes included in the
|
|
|
|
* request.
|
|
|
|
*
|
|
|
|
* So CRS in this case is not an error status.
|
|
|
|
*/
|
|
|
|
*val = CFG_RD_CRS_VAL;
|
|
|
|
strcomp_status = NULL;
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = 0;
|
2021-07-22 14:40:41 +00:00
|
|
|
break;
|
|
|
|
}
|
2021-07-22 14:40:38 +00:00
|
|
|
/* PCIe r4.0, sec 2.3.2, says:
|
|
|
|
* If CRS Software Visibility is not enabled, the Root Complex
|
|
|
|
* must re-issue the Configuration Request as a new Request.
|
2021-07-22 14:40:41 +00:00
|
|
|
* If CRS Software Visibility is enabled: For a Configuration
|
|
|
|
* Write Request or for any other Configuration Read Request,
|
|
|
|
* the Root Complex must re-issue the Configuration Request as
|
|
|
|
* a new Request.
|
2021-07-22 14:40:38 +00:00
|
|
|
* A Root Complex implementation may choose to limit the number
|
|
|
|
* of Configuration Request/CRS Completion Status loops before
|
|
|
|
* determining that something is wrong with the target of the
|
|
|
|
* Request and taking appropriate action, e.g., complete the
|
|
|
|
* Request to the host as a failed transaction.
|
|
|
|
*
|
2021-10-05 18:09:48 +00:00
|
|
|
* So return -EAGAIN and caller (pci-aardvark.c driver) will
|
|
|
|
* re-issue request again up to the PIO_RETRY_CNT retries.
|
2021-07-22 14:40:38 +00:00
|
|
|
*/
|
2016-06-30 09:32:31 +00:00
|
|
|
strcomp_status = "CRS";
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = -EAGAIN;
|
2016-06-30 09:32:31 +00:00
|
|
|
break;
|
|
|
|
case PIO_COMPLETION_STATUS_CA:
|
|
|
|
strcomp_status = "CA";
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = -ECANCELED;
|
2016-06-30 09:32:31 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
strcomp_status = "Unknown";
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = -EINVAL;
|
2016-06-30 09:32:31 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2021-07-22 14:40:38 +00:00
|
|
|
if (!strcomp_status)
|
2021-10-05 18:09:48 +00:00
|
|
|
return ret;
|
2021-07-22 14:40:38 +00:00
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
if (reg & PIO_NON_POSTED_REQ)
|
|
|
|
str_posted = "Non-posted";
|
|
|
|
else
|
|
|
|
str_posted = "Posted";
|
|
|
|
|
2021-10-05 18:09:42 +00:00
|
|
|
dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
|
2016-06-30 09:32:31 +00:00
|
|
|
str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
|
2021-07-22 14:40:38 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
return ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_wait_pio(struct advk_pcie *pcie)
|
|
|
|
{
|
2016-10-06 18:27:46 +00:00
|
|
|
struct device *dev = &pcie->pdev->dev;
|
2019-09-27 08:55:02 +00:00
|
|
|
int i;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
for (i = 1; i <= PIO_RETRY_CNT; i++) {
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 start, isr;
|
|
|
|
|
|
|
|
start = advk_readl(pcie, PIO_START);
|
|
|
|
isr = advk_readl(pcie, PIO_ISR);
|
|
|
|
if (!start && isr)
|
2021-10-05 18:09:48 +00:00
|
|
|
return i;
|
2019-09-27 08:55:02 +00:00
|
|
|
udelay(PIO_RETRY_DELAY);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2021-06-08 20:36:55 +00:00
|
|
|
dev_err(dev, "PIO read/write transfer time out\n");
|
2016-06-30 09:32:31 +00:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2021-10-28 18:56:56 +00:00
|
|
|
static pci_bridge_emul_read_status_t
|
|
|
|
advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
|
|
|
|
int reg, u32 *value)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bridge->data;
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case PCI_COMMAND:
|
|
|
|
*value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
|
|
|
|
2021-10-28 18:56:58 +00:00
|
|
|
case PCI_INTERRUPT_LINE: {
|
|
|
|
/*
|
|
|
|
* From the whole 32bit register we support reading from HW only
|
2022-01-10 01:50:08 +00:00
|
|
|
* two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR.
|
2021-10-28 18:56:58 +00:00
|
|
|
* Other bits are retrieved only from emulated config buffer.
|
|
|
|
*/
|
|
|
|
__le32 *cfgspace = (__le32 *)&bridge->conf;
|
|
|
|
u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
|
2022-01-10 01:50:08 +00:00
|
|
|
if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)
|
|
|
|
val &= ~(PCI_BRIDGE_CTL_SERR << 16);
|
|
|
|
else
|
|
|
|
val |= PCI_BRIDGE_CTL_SERR << 16;
|
2021-10-28 18:56:58 +00:00
|
|
|
if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
|
|
|
|
val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
|
|
|
|
else
|
|
|
|
val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
|
|
|
|
*value = val;
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
|
|
|
}
|
|
|
|
|
2021-10-28 18:56:56 +00:00
|
|
|
default:
|
|
|
|
return PCI_BRIDGE_EMUL_NOT_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
|
|
|
|
int reg, u32 old, u32 new, u32 mask)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bridge->data;
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case PCI_COMMAND:
|
|
|
|
advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
break;
|
|
|
|
|
2021-10-28 18:56:58 +00:00
|
|
|
case PCI_INTERRUPT_LINE:
|
2022-01-10 01:50:08 +00:00
|
|
|
/*
|
|
|
|
* According to Figure 6-3: Pseudo Logic Diagram for Error
|
|
|
|
* Message Controls in PCIe base specification, SERR# Enable bit
|
|
|
|
* in Bridge Control register enable receiving of ERR_* messages
|
|
|
|
*/
|
|
|
|
if (mask & (PCI_BRIDGE_CTL_SERR << 16)) {
|
|
|
|
u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
|
|
|
if (new & (PCI_BRIDGE_CTL_SERR << 16))
|
|
|
|
val &= ~PCIE_ISR0_ERR_MASK;
|
|
|
|
else
|
|
|
|
val |= PCIE_ISR0_ERR_MASK;
|
|
|
|
advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
|
|
|
|
}
|
2021-10-28 18:56:58 +00:00
|
|
|
if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
|
|
|
|
u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
|
|
|
|
if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
|
|
|
|
val |= HOT_RESET_GEN;
|
|
|
|
else
|
|
|
|
val &= ~HOT_RESET_GEN;
|
|
|
|
advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2021-10-28 18:56:56 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2018-10-18 15:37:19 +00:00
|
|
|
|
|
|
|
static pci_bridge_emul_read_status_t
|
|
|
|
advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
|
|
|
|
int reg, u32 *value)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bridge->data;
|
|
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case PCI_EXP_SLTCTL:
|
|
|
|
*value = PCI_EXP_SLTSTA_PDS << 16;
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
/*
|
|
|
|
* PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need
|
|
|
|
* to be handled here, because their values are stored in emulated
|
|
|
|
* config space buffer, and we read them from there when needed.
|
|
|
|
*/
|
2018-10-18 15:37:19 +00:00
|
|
|
|
2021-10-05 18:09:52 +00:00
|
|
|
case PCI_EXP_LNKCAP: {
|
|
|
|
u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
|
|
|
|
/*
|
|
|
|
* PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.
|
|
|
|
* But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm
|
|
|
|
* state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag.
|
|
|
|
*/
|
|
|
|
val |= PCI_EXP_LNKCAP_DLLLARC;
|
|
|
|
*value = val;
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
|
|
|
}
|
|
|
|
|
2019-05-22 21:33:51 +00:00
|
|
|
case PCI_EXP_LNKCTL: {
|
|
|
|
/* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
|
|
|
|
u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
|
|
|
|
~(PCI_EXP_LNKSTA_LT << 16);
|
2021-10-05 18:09:51 +00:00
|
|
|
if (advk_pcie_link_training(pcie))
|
2019-05-22 21:33:51 +00:00
|
|
|
val |= (PCI_EXP_LNKSTA_LT << 16);
|
2021-10-05 18:09:52 +00:00
|
|
|
if (advk_pcie_link_active(pcie))
|
|
|
|
val |= (PCI_EXP_LNKSTA_DLLLA << 16);
|
2019-05-22 21:33:51 +00:00
|
|
|
*value = val;
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
|
|
|
}
|
|
|
|
|
2018-10-18 15:37:19 +00:00
|
|
|
case PCI_EXP_DEVCAP:
|
|
|
|
case PCI_EXP_DEVCTL:
|
2021-11-30 17:29:05 +00:00
|
|
|
case PCI_EXP_DEVCAP2:
|
|
|
|
case PCI_EXP_DEVCTL2:
|
|
|
|
case PCI_EXP_LNKCAP2:
|
|
|
|
case PCI_EXP_LNKCTL2:
|
2018-10-18 15:37:19 +00:00
|
|
|
*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
|
|
|
|
return PCI_BRIDGE_EMUL_HANDLED;
|
2021-11-30 17:29:05 +00:00
|
|
|
|
2018-10-18 15:37:19 +00:00
|
|
|
default:
|
|
|
|
return PCI_BRIDGE_EMUL_NOT_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
|
|
|
|
int reg, u32 old, u32 new, u32 mask)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bridge->data;
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case PCI_EXP_LNKCTL:
|
|
|
|
advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
|
2019-05-22 21:33:51 +00:00
|
|
|
if (new & PCI_EXP_LNKCTL_RL)
|
|
|
|
advk_pcie_wait_for_retrain(pcie);
|
2018-10-18 15:37:19 +00:00
|
|
|
break;
|
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
case PCI_EXP_RTCTL: {
|
|
|
|
u16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl);
|
|
|
|
/* Only emulation of PMEIE and CRSSVE bits is provided */
|
|
|
|
rootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE;
|
|
|
|
bridge->pcie_conf.rootctl = cpu_to_le16(rootctl);
|
2018-10-18 15:37:19 +00:00
|
|
|
break;
|
2022-01-10 01:50:12 +00:00
|
|
|
}
|
2018-10-18 15:37:19 +00:00
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
/*
|
|
|
|
* PCI_EXP_RTSTA is also supported, but does not need to be handled
|
|
|
|
* here, because its value is stored in emulated config space buffer,
|
|
|
|
* and we write it there when needed.
|
|
|
|
*/
|
2018-10-18 15:37:19 +00:00
|
|
|
|
2021-11-30 17:29:05 +00:00
|
|
|
case PCI_EXP_DEVCTL:
|
|
|
|
case PCI_EXP_DEVCTL2:
|
|
|
|
case PCI_EXP_LNKCTL2:
|
|
|
|
advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
|
|
|
|
break;
|
|
|
|
|
2018-10-18 15:37:19 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-03-01 06:58:09 +00:00
|
|
|
static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
|
2021-10-28 18:56:56 +00:00
|
|
|
.read_base = advk_pci_bridge_emul_base_conf_read,
|
|
|
|
.write_base = advk_pci_bridge_emul_base_conf_write,
|
2018-10-18 15:37:19 +00:00
|
|
|
.read_pcie = advk_pci_bridge_emul_pcie_conf_read,
|
|
|
|
.write_pcie = advk_pci_bridge_emul_pcie_conf_write,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the configuration space of the PCI-to-PCI bridge
|
|
|
|
* associated with the given PCIe interface.
|
|
|
|
*/
|
2020-09-07 11:10:35 +00:00
|
|
|
static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
|
2018-10-18 15:37:19 +00:00
|
|
|
{
|
|
|
|
struct pci_bridge_emul *bridge = &pcie->bridge;
|
|
|
|
|
2019-07-16 12:12:07 +00:00
|
|
|
bridge->conf.vendor =
|
|
|
|
cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
|
|
|
|
bridge->conf.device =
|
|
|
|
cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
|
2018-10-18 15:37:19 +00:00
|
|
|
bridge->conf.class_revision =
|
2019-07-16 12:12:07 +00:00
|
|
|
cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
|
2018-10-18 15:37:19 +00:00
|
|
|
|
|
|
|
/* Support 32 bits I/O addressing */
|
|
|
|
bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
|
|
|
|
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
|
|
|
|
|
|
|
|
/* Support 64 bits memory pref */
|
2019-07-16 12:12:07 +00:00
|
|
|
bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
|
|
|
|
bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
|
2018-10-18 15:37:19 +00:00
|
|
|
|
|
|
|
/* Support interrupt A for MSI feature */
|
2022-01-10 01:49:56 +00:00
|
|
|
bridge->conf.intpin = PCI_INTERRUPT_INTA;
|
2018-10-18 15:37:19 +00:00
|
|
|
|
2021-11-24 15:59:43 +00:00
|
|
|
/* Aardvark HW provides PCIe Capability structure in version 2 */
|
|
|
|
bridge->pcie_conf.cap = cpu_to_le16(2);
|
|
|
|
|
2021-10-05 18:09:49 +00:00
|
|
|
/* Indicates supports for Completion Retry Status */
|
|
|
|
bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
|
|
|
|
|
2018-10-18 15:37:19 +00:00
|
|
|
bridge->has_pcie = true;
|
|
|
|
bridge->data = pcie;
|
|
|
|
bridge->ops = &advk_pci_bridge_emul_ops;
|
|
|
|
|
2021-10-05 18:09:49 +00:00
|
|
|
return pci_bridge_emul_init(bridge, 0);
|
2018-10-18 15:37:19 +00:00
|
|
|
}
|
|
|
|
|
2018-04-06 14:55:35 +00:00
|
|
|
static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
|
|
|
|
int devfn)
|
|
|
|
{
|
2020-07-22 02:24:59 +00:00
|
|
|
if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
|
2018-04-06 14:55:35 +00:00
|
|
|
return false;
|
|
|
|
|
2020-07-02 08:30:36 +00:00
|
|
|
/*
|
|
|
|
* If the link goes down after we check for link-up, nothing bad
|
|
|
|
* happens but the config access times out.
|
|
|
|
*/
|
Merge branch 'pci/host-probe-refactor'
- Use pci_host_bridge.windows list directly instead of splicing in a
temporary list for cadence, mvebu, host-common (Rob Herring)
- Use pci_host_probe() instead of open-coding all the pieces for altera,
brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene,
xilinx, xilinx-nwl (Rob Herring)
- Convert to devm_platform_ioremap_resource_byname() instead of open-coding
platform_get_resource_byname() and devm_ioremap_resource() for altera,
cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng)
- Convert to devm_platform_ioremap_resource() instead of open-coding
platform_get_resource() and devm_ioremap_resource() for aardvark,
brcmstb, exynos, ftpci100, versatile (Dejin Zheng)
- Remove redundant error messages from devm_pci_remap_cfg_resource()
callers (Dejin Zheng)
- Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring)
- Default host bridge parent device to the platform device (Rob Herring)
- Drop unnecessary zeroing of host bridge fields (Rob Herring)
- Use pci_is_root_bus() instead of tracking root bus number separately in
aardvark, designware (imx6, keystone, designware-host), mobiveil,
xilinx-nwl, xilinx, rockchip, rcar (Rob Herring)
- Set host bridge bus number in pci_scan_root_bus_bridge() instead of each
driver for aardvark, designware-host, host-common, mediatek, rcar, tegra,
v3-semi (Rob Herring)
- Use bridge resources instead of parsing DT 'ranges' again for cadence
(Rob Herring)
- Remove private bus number and range from cadence (Rob Herring)
- Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring)
- Use struct pci_host_bridge.windows list directly rather than a temporary
(Rob Herring)
- Reduce OF "missing non-prefetchable window" from error to warning message
(Rob Herring)
- Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new
arch-independent interfaces (Rob Herring)
- Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring)
- Set bridge map_irq and swizzle_irq to default functions; drivers that
don't support legacy IRQs (iproc) need to undo this (Rob Herring)
* pci/host-probe-refactor:
PCI: Set bridge map_irq and swizzle_irq to default functions
PCI: Move DT resource setup into devm_pci_alloc_host_bridge()
PCI: rcar-gen2: Convert to use modern host bridge probe functions
PCI: of: Reduce missing non-prefetchable memory region to a warning
PCI: rcar: Use struct pci_host_bridge.windows list directly
PCI: rcar: Use devm_pci_alloc_host_bridge()
PCI: cadence: Remove private bus number and range storage
PCI: cadence: Use bridge resources for outbound window setup
PCI: Move setting pci_host_bridge.busnr out of host drivers
PCI: rcar: Use pci_is_root_bus() to check if bus is root bus
PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus
PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus
PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus
PCI: designware: Use pci_is_root_bus() to check if bus is root bus
PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus
PCI: Drop unnecessary zeroing of bridge fields
PCI: Set default bridge parent device
PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS
PCI: controller: Remove duplicate error message
PCI: controller: Convert to devm_platform_ioremap_resource()
PCI: controller: Convert to devm_platform_ioremap_resource_byname()
PCI: xilinx: Use pci_host_probe() to register host
PCI: xilinx-nwl: Use pci_host_probe() to register host
PCI: rockchip: Use pci_host_probe() to register host
PCI: rcar: Use pci_host_probe() to register host
PCI: iproc: Use pci_host_probe() to register host
PCI: altera: Use pci_host_probe() to register host
PCI: xgene: Use pci_host_probe() to register host
PCI: versatile: Use pci_host_probe() to register host
PCI: v3: Use pci_host_probe() to register host
PCI: tegra: Use pci_host_probe() to register host
PCI: mobiveil: Use pci_host_probe() to register host
PCI: brcmstb: Use pci_host_probe() to register host
PCI: host-common: Use struct pci_host_bridge.windows list directly
PCI: mvebu: Use struct pci_host_bridge.windows list directly
PCI: cadence: Use struct pci_host_bridge.windows list directly
# Conflicts:
# drivers/pci/controller/cadence/pcie-cadence-host.c
2020-08-05 23:24:21 +00:00
|
|
|
if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
|
2020-07-02 08:30:36 +00:00
|
|
|
return false;
|
|
|
|
|
2018-04-06 14:55:35 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-06-08 20:36:55 +00:00
|
|
|
static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Trying to start a new PIO transfer when previous has not completed
|
|
|
|
* cause External Abort on CPU which results in kernel panic:
|
|
|
|
*
|
|
|
|
* SError Interrupt on CPU0, code 0xbf000002 -- SError
|
|
|
|
* Kernel panic - not syncing: Asynchronous SError Interrupt
|
|
|
|
*
|
|
|
|
* Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
|
|
|
|
* by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
|
|
|
|
* concurrent calls at the same time. But because PIO transfer may take
|
|
|
|
* about 1.5s when link is down or card is disconnected, it means that
|
|
|
|
* advk_pcie_wait_pio() does not always have to wait for completion.
|
|
|
|
*
|
|
|
|
* Some versions of ARM Trusted Firmware handles this External Abort at
|
|
|
|
* EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
|
|
|
|
* https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
|
|
|
|
*/
|
|
|
|
if (advk_readl(pcie, PIO_START)) {
|
|
|
|
dev_err(dev, "Previous PIO read/write transfer is still running\n");
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
|
|
|
|
int where, int size, u32 *val)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bus->sysdata;
|
2021-10-05 18:09:48 +00:00
|
|
|
int retry_count;
|
2021-07-22 14:40:41 +00:00
|
|
|
bool allow_crs;
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
|
2021-11-18 14:03:21 +00:00
|
|
|
if (!advk_pcie_valid_device(pcie, bus, devfn))
|
2016-06-30 09:32:31 +00:00
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
2020-07-22 02:24:59 +00:00
|
|
|
if (pci_is_root_bus(bus))
|
2018-10-18 15:37:19 +00:00
|
|
|
return pci_bridge_emul_conf_read(&pcie->bridge, where,
|
|
|
|
size, val);
|
|
|
|
|
2021-07-22 14:40:41 +00:00
|
|
|
/*
|
|
|
|
* Completion Retry Status is possible to return only when reading all
|
|
|
|
* 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and
|
|
|
|
* CRSSVE flag on Root Bridge is enabled.
|
|
|
|
*/
|
|
|
|
allow_crs = (where == PCI_VENDOR_ID) && (size == 4) &&
|
|
|
|
(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) &
|
|
|
|
PCI_EXP_RTCTL_CRSSVE);
|
|
|
|
|
2021-10-05 18:09:47 +00:00
|
|
|
if (advk_pcie_pio_is_running(pcie))
|
|
|
|
goto try_crs;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
/* Program the control register */
|
|
|
|
reg = advk_readl(pcie, PIO_CTRL);
|
|
|
|
reg &= ~PIO_CTRL_TYPE_MASK;
|
2020-07-22 02:24:59 +00:00
|
|
|
if (pci_is_root_bus(bus->parent))
|
2016-06-30 09:32:31 +00:00
|
|
|
reg |= PCIE_CONFIG_RD_TYPE0;
|
|
|
|
else
|
|
|
|
reg |= PCIE_CONFIG_RD_TYPE1;
|
|
|
|
advk_writel(pcie, reg, PIO_CTRL);
|
|
|
|
|
|
|
|
/* Program the address registers */
|
2020-11-29 23:07:39 +00:00
|
|
|
reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_writel(pcie, reg, PIO_ADDR_LS);
|
|
|
|
advk_writel(pcie, 0, PIO_ADDR_MS);
|
|
|
|
|
|
|
|
/* Program the data strobe */
|
|
|
|
advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
|
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
retry_count = 0;
|
|
|
|
do {
|
|
|
|
/* Clear PIO DONE ISR and start the transfer */
|
|
|
|
advk_writel(pcie, 1, PIO_ISR);
|
|
|
|
advk_writel(pcie, 1, PIO_START);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = advk_pcie_wait_pio(pcie);
|
|
|
|
if (ret < 0)
|
|
|
|
goto try_crs;
|
|
|
|
|
|
|
|
retry_count += ret;
|
|
|
|
|
|
|
|
/* Check PIO status and get the read result */
|
|
|
|
ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
|
|
|
|
} while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:47 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto fail;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
if (size == 1)
|
|
|
|
*val = (*val >> (8 * (where & 3))) & 0xff;
|
|
|
|
else if (size == 2)
|
|
|
|
*val = (*val >> (8 * (where & 3))) & 0xffff;
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
2021-10-05 18:09:47 +00:00
|
|
|
|
|
|
|
try_crs:
|
|
|
|
/*
|
|
|
|
* If it is possible, return Completion Retry Status so that caller
|
|
|
|
* tries to issue the request again instead of failing.
|
|
|
|
*/
|
|
|
|
if (allow_crs) {
|
|
|
|
*val = CFG_RD_CRS_VAL;
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
fail:
|
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_SET_FAILED;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
|
|
int where, int size, u32 val)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = bus->sysdata;
|
|
|
|
u32 reg;
|
|
|
|
u32 data_strobe = 0x0;
|
2021-10-05 18:09:48 +00:00
|
|
|
int retry_count;
|
2016-06-30 09:32:31 +00:00
|
|
|
int offset;
|
|
|
|
int ret;
|
|
|
|
|
2018-04-06 14:55:35 +00:00
|
|
|
if (!advk_pcie_valid_device(pcie, bus, devfn))
|
2016-06-30 09:32:31 +00:00
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
2020-07-22 02:24:59 +00:00
|
|
|
if (pci_is_root_bus(bus))
|
2018-10-18 15:37:19 +00:00
|
|
|
return pci_bridge_emul_conf_write(&pcie->bridge, where,
|
|
|
|
size, val);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
if (where % size)
|
|
|
|
return PCIBIOS_SET_FAILED;
|
|
|
|
|
2021-06-08 20:36:55 +00:00
|
|
|
if (advk_pcie_pio_is_running(pcie))
|
|
|
|
return PCIBIOS_SET_FAILED;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
/* Program the control register */
|
|
|
|
reg = advk_readl(pcie, PIO_CTRL);
|
|
|
|
reg &= ~PIO_CTRL_TYPE_MASK;
|
2020-07-22 02:24:59 +00:00
|
|
|
if (pci_is_root_bus(bus->parent))
|
2016-06-30 09:32:31 +00:00
|
|
|
reg |= PCIE_CONFIG_WR_TYPE0;
|
|
|
|
else
|
|
|
|
reg |= PCIE_CONFIG_WR_TYPE1;
|
|
|
|
advk_writel(pcie, reg, PIO_CTRL);
|
|
|
|
|
|
|
|
/* Program the address registers */
|
2020-11-29 23:07:39 +00:00
|
|
|
reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_writel(pcie, reg, PIO_ADDR_LS);
|
|
|
|
advk_writel(pcie, 0, PIO_ADDR_MS);
|
|
|
|
|
|
|
|
/* Calculate the write strobe */
|
|
|
|
offset = where & 0x3;
|
|
|
|
reg = val << (8 * offset);
|
|
|
|
data_strobe = GENMASK(size - 1, 0) << offset;
|
|
|
|
|
|
|
|
/* Program the data register */
|
|
|
|
advk_writel(pcie, reg, PIO_WR_DATA);
|
|
|
|
|
|
|
|
/* Program the data strobe */
|
|
|
|
advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
|
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
retry_count = 0;
|
|
|
|
do {
|
|
|
|
/* Clear PIO DONE ISR and start the transfer */
|
|
|
|
advk_writel(pcie, 1, PIO_ISR);
|
|
|
|
advk_writel(pcie, 1, PIO_START);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = advk_pcie_wait_pio(pcie);
|
|
|
|
if (ret < 0)
|
|
|
|
return PCIBIOS_SET_FAILED;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
retry_count += ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-05 18:09:48 +00:00
|
|
|
ret = advk_pcie_check_pio_status(pcie, false, NULL);
|
|
|
|
} while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
|
|
|
|
|
|
|
|
return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_ops advk_pcie_ops = {
|
|
|
|
.read = advk_pcie_rd_conf,
|
|
|
|
.write = advk_pcie_wr_conf,
|
|
|
|
};
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
|
|
|
|
struct msi_msg *msg)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2017-02-28 14:31:14 +00:00
|
|
|
struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
|
2022-01-10 01:50:06 +00:00
|
|
|
phys_addr_t msi_addr = virt_to_phys(pcie);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:50:06 +00:00
|
|
|
msg->address_lo = lower_32_bits(msi_addr);
|
|
|
|
msg->address_hi = upper_32_bits(msi_addr);
|
2022-01-10 01:49:58 +00:00
|
|
|
msg->data = data->hwirq;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
static int advk_msi_set_affinity(struct irq_data *irq_data,
|
|
|
|
const struct cpumask *mask, bool force)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2017-02-28 14:31:14 +00:00
|
|
|
return -EINVAL;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:05 +00:00
|
|
|
static void advk_msi_irq_mask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = d->domain->host_data;
|
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
|
|
unsigned long flags;
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
|
|
|
|
mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
|
|
|
|
mask |= BIT(hwirq);
|
|
|
|
advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
|
|
|
|
raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_msi_irq_unmask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = d->domain->host_data;
|
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
|
|
|
unsigned long flags;
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
|
|
|
|
mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
|
|
|
|
mask &= ~BIT(hwirq);
|
|
|
|
advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
|
|
|
|
raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_msi_top_irq_mask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
pci_msi_mask_irq(d);
|
|
|
|
irq_chip_mask_parent(d);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_msi_top_irq_unmask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
pci_msi_unmask_irq(d);
|
|
|
|
irq_chip_unmask_parent(d);
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:01 +00:00
|
|
|
static struct irq_chip advk_msi_bottom_irq_chip = {
|
|
|
|
.name = "MSI",
|
|
|
|
.irq_compose_msi_msg = advk_msi_irq_compose_msi_msg,
|
|
|
|
.irq_set_affinity = advk_msi_set_affinity,
|
2022-01-10 01:50:05 +00:00
|
|
|
.irq_mask = advk_msi_irq_mask,
|
|
|
|
.irq_unmask = advk_msi_irq_unmask,
|
2022-01-10 01:50:01 +00:00
|
|
|
};
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
|
|
|
|
unsigned int virq,
|
|
|
|
unsigned int nr_irqs, void *args)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2017-02-28 14:31:14 +00:00
|
|
|
struct advk_pcie *pcie = domain->host_data;
|
|
|
|
int hwirq, i;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
mutex_lock(&pcie->msi_used_lock);
|
2022-01-10 01:49:58 +00:00
|
|
|
hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM,
|
|
|
|
order_base_2(nr_irqs));
|
2017-02-28 14:31:14 +00:00
|
|
|
mutex_unlock(&pcie->msi_used_lock);
|
2022-01-10 01:49:58 +00:00
|
|
|
if (hwirq < 0)
|
|
|
|
return -ENOSPC;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
|
|
irq_domain_set_info(domain, virq + i, hwirq + i,
|
2022-01-10 01:50:01 +00:00
|
|
|
&advk_msi_bottom_irq_chip,
|
2017-02-28 14:31:14 +00:00
|
|
|
domain->host_data, handle_simple_irq,
|
|
|
|
NULL, NULL);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-10-28 18:56:54 +00:00
|
|
|
return 0;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
static void advk_msi_irq_domain_free(struct irq_domain *domain,
|
|
|
|
unsigned int virq, unsigned int nr_irqs)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2017-02-28 14:31:14 +00:00
|
|
|
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
2016-06-30 09:32:31 +00:00
|
|
|
struct advk_pcie *pcie = domain->host_data;
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
mutex_lock(&pcie->msi_used_lock);
|
2022-01-10 01:49:58 +00:00
|
|
|
bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs));
|
2017-02-28 14:31:14 +00:00
|
|
|
mutex_unlock(&pcie->msi_used_lock);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
static const struct irq_domain_ops advk_msi_domain_ops = {
|
|
|
|
.alloc = advk_msi_irq_domain_alloc,
|
|
|
|
.free = advk_msi_irq_domain_free,
|
2016-06-30 09:32:31 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static void advk_pcie_irq_mask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = d->domain->host_data;
|
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2021-08-20 15:50:20 +00:00
|
|
|
unsigned long flags;
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 mask;
|
|
|
|
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spin_lock_irqsave(&pcie->irq_lock, flags);
|
2018-04-06 14:55:33 +00:00
|
|
|
mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
|
|
|
|
mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
|
|
|
|
advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_irq_unmask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = d->domain->host_data;
|
|
|
|
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
2021-08-20 15:50:20 +00:00
|
|
|
unsigned long flags;
|
2016-06-30 09:32:31 +00:00
|
|
|
u32 mask;
|
|
|
|
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spin_lock_irqsave(&pcie->irq_lock, flags);
|
2018-04-06 14:55:33 +00:00
|
|
|
mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
|
|
|
|
mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
|
|
|
|
advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_irq_map(struct irq_domain *h,
|
|
|
|
unsigned int virq, irq_hw_number_t hwirq)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = h->host_data;
|
|
|
|
|
|
|
|
irq_set_status_flags(virq, IRQ_LEVEL);
|
|
|
|
irq_set_chip_and_handler(virq, &pcie->irq_chip,
|
|
|
|
handle_level_irq);
|
|
|
|
irq_set_chip_data(virq, pcie);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
|
|
|
|
.map = advk_pcie_irq_map,
|
|
|
|
.xlate = irq_domain_xlate_onecell,
|
|
|
|
};
|
|
|
|
|
2022-01-10 01:50:01 +00:00
|
|
|
static struct irq_chip advk_msi_irq_chip = {
|
2022-01-10 01:50:05 +00:00
|
|
|
.name = "advk-MSI",
|
|
|
|
.irq_mask = advk_msi_top_irq_mask,
|
|
|
|
.irq_unmask = advk_msi_top_irq_unmask,
|
2022-01-10 01:50:01 +00:00
|
|
|
};
|
|
|
|
|
2022-01-10 01:50:02 +00:00
|
|
|
static struct msi_domain_info advk_msi_domain_info = {
|
|
|
|
.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
|
2022-01-10 01:50:07 +00:00
|
|
|
MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
|
2022-01-10 01:50:02 +00:00
|
|
|
.chip = &advk_msi_irq_chip,
|
|
|
|
};
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
|
2022-01-10 01:50:05 +00:00
|
|
|
raw_spin_lock_init(&pcie->msi_irq_lock);
|
2017-02-28 14:31:14 +00:00
|
|
|
mutex_init(&pcie->msi_used_lock);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
pcie->msi_inner_domain =
|
2016-06-30 09:32:31 +00:00
|
|
|
irq_domain_add_linear(NULL, MSI_IRQ_NUM,
|
2017-02-28 14:31:14 +00:00
|
|
|
&advk_msi_domain_ops, pcie);
|
|
|
|
if (!pcie->msi_inner_domain)
|
2016-06-30 09:32:31 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-02-28 14:31:14 +00:00
|
|
|
pcie->msi_domain =
|
2022-01-10 01:50:03 +00:00
|
|
|
pci_msi_create_irq_domain(dev_fwnode(dev),
|
2022-01-10 01:50:02 +00:00
|
|
|
&advk_msi_domain_info,
|
|
|
|
pcie->msi_inner_domain);
|
2017-02-28 14:31:14 +00:00
|
|
|
if (!pcie->msi_domain) {
|
|
|
|
irq_domain_remove(pcie->msi_inner_domain);
|
|
|
|
return -ENOMEM;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
irq_domain_remove(pcie->msi_domain);
|
2017-02-28 14:31:14 +00:00
|
|
|
irq_domain_remove(pcie->msi_inner_domain);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
struct device_node *node = dev->of_node;
|
|
|
|
struct device_node *pcie_intc_node;
|
|
|
|
struct irq_chip *irq_chip;
|
2019-02-27 04:40:40 +00:00
|
|
|
int ret = 0;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-08-20 15:50:20 +00:00
|
|
|
raw_spin_lock_init(&pcie->irq_lock);
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
pcie_intc_node = of_get_next_child(node, NULL);
|
|
|
|
if (!pcie_intc_node) {
|
|
|
|
dev_err(dev, "No PCIe Intc node found\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq_chip = &pcie->irq_chip;
|
|
|
|
|
|
|
|
irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
|
|
|
|
dev_name(dev));
|
|
|
|
if (!irq_chip->name) {
|
2019-02-27 04:40:40 +00:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out_put_node;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
irq_chip->irq_mask = advk_pcie_irq_mask;
|
|
|
|
irq_chip->irq_unmask = advk_pcie_irq_unmask;
|
|
|
|
|
|
|
|
pcie->irq_domain =
|
2017-08-15 21:26:03 +00:00
|
|
|
irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
|
2016-06-30 09:32:31 +00:00
|
|
|
&advk_pcie_irq_domain_ops, pcie);
|
|
|
|
if (!pcie->irq_domain) {
|
|
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
2019-02-27 04:40:40 +00:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out_put_node;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2019-02-27 04:40:40 +00:00
|
|
|
out_put_node:
|
|
|
|
of_node_put(pcie_intc_node);
|
|
|
|
return ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
irq_domain_remove(pcie->irq_domain);
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:13 +00:00
|
|
|
static struct irq_chip advk_rp_irq_chip = {
|
|
|
|
.name = "advk-RP",
|
|
|
|
};
|
|
|
|
|
|
|
|
static int advk_pcie_rp_irq_map(struct irq_domain *h,
|
|
|
|
unsigned int virq, irq_hw_number_t hwirq)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = h->host_data;
|
|
|
|
|
|
|
|
irq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq);
|
|
|
|
irq_set_chip_data(virq, pcie);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = {
|
|
|
|
.map = advk_pcie_rp_irq_map,
|
|
|
|
.xlate = irq_domain_xlate_onecell,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1,
|
|
|
|
&advk_pcie_rp_irq_domain_ops,
|
|
|
|
pcie);
|
|
|
|
if (!pcie->rp_irq_domain) {
|
|
|
|
dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
irq_domain_remove(pcie->rp_irq_domain);
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
static void advk_pcie_handle_pme(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
|
|
|
|
|
|
|
|
advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PCIE_MSG_LOG_REG contains the last inbound message, so store
|
|
|
|
* the requester ID only when PME was not asserted yet.
|
|
|
|
* Also do not trigger PME interrupt when PME is still asserted.
|
|
|
|
*/
|
|
|
|
if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {
|
|
|
|
pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Trigger PME interrupt only if PMEIE bit in Root Control is set.
|
|
|
|
* Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.
|
|
|
|
*/
|
|
|
|
if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))
|
|
|
|
return;
|
|
|
|
|
2022-01-10 01:50:13 +00:00
|
|
|
if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)
|
2022-01-10 01:50:12 +00:00
|
|
|
dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static void advk_pcie_handle_msi(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
u32 msi_val, msi_mask, msi_status, msi_idx;
|
|
|
|
|
|
|
|
msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
|
|
|
|
msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
|
2021-11-30 17:29:06 +00:00
|
|
|
msi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
|
|
|
|
if (!(BIT(msi_idx) & msi_status))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
|
2022-01-10 01:49:57 +00:00
|
|
|
if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL)
|
|
|
|
dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
|
|
|
|
PCIE_ISR0_REG);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void advk_pcie_handle_int(struct advk_pcie *pcie)
|
|
|
|
{
|
2018-04-06 14:55:33 +00:00
|
|
|
u32 isr0_val, isr0_mask, isr0_status;
|
|
|
|
u32 isr1_val, isr1_mask, isr1_status;
|
2021-08-02 16:26:19 +00:00
|
|
|
int i;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2018-04-06 14:55:33 +00:00
|
|
|
isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
|
|
|
|
isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
|
|
|
|
isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2018-04-06 14:55:33 +00:00
|
|
|
isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
|
|
|
|
isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
|
|
|
|
isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
|
|
|
|
|
2022-01-10 01:50:12 +00:00
|
|
|
/* Process PME interrupt as the first one to do not miss PME requester id */
|
|
|
|
if (isr0_status & PCIE_MSG_PM_PME_MASK)
|
|
|
|
advk_pcie_handle_pme(pcie);
|
2022-01-10 01:50:11 +00:00
|
|
|
|
2022-01-10 01:50:08 +00:00
|
|
|
/* Process ERR interrupt */
|
|
|
|
if (isr0_status & PCIE_ISR0_ERR_MASK) {
|
|
|
|
advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use
|
|
|
|
* PCIe interrupt 0
|
|
|
|
*/
|
2022-01-10 01:50:13 +00:00
|
|
|
if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)
|
2022-01-10 01:50:08 +00:00
|
|
|
dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n");
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
/* Process MSI interrupts */
|
2018-04-06 14:55:33 +00:00
|
|
|
if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_pcie_handle_msi(pcie);
|
|
|
|
|
|
|
|
/* Process legacy interrupts */
|
2017-08-15 21:26:03 +00:00
|
|
|
for (i = 0; i < PCI_NUM_INTX; i++) {
|
2018-04-06 14:55:33 +00:00
|
|
|
if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
|
2016-06-30 09:32:31 +00:00
|
|
|
continue;
|
|
|
|
|
2018-04-06 14:55:33 +00:00
|
|
|
advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
|
|
|
|
PCIE_ISR1_REG);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:50:00 +00:00
|
|
|
if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL)
|
|
|
|
dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n",
|
|
|
|
(char)i + 'A');
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
static void advk_pcie_irq_handler(struct irq_desc *desc)
|
2016-06-30 09:32:31 +00:00
|
|
|
{
|
2022-01-10 01:49:59 +00:00
|
|
|
struct advk_pcie *pcie = irq_desc_get_handler_data(desc);
|
|
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
u32 val, mask, status;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
chained_irq_enter(chip, desc);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
val = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
|
|
|
|
mask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG);
|
|
|
|
status = val & ((~mask) & PCIE_IRQ_ALL_MASK);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
if (status & PCIE_IRQ_CORE_INT) {
|
|
|
|
advk_pcie_handle_int(pcie);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
/* Clear interrupt */
|
|
|
|
advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
|
|
|
|
}
|
|
|
|
|
|
|
|
chained_irq_exit(chip, desc);
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:13 +00:00
|
|
|
static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = dev->bus->sysdata;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Emulated root bridge has its own emulated irq chip and irq domain.
|
|
|
|
* Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and
|
|
|
|
* hwirq for irq_create_mapping() is indexed from zero.
|
|
|
|
*/
|
|
|
|
if (pci_is_root_bus(dev->bus))
|
|
|
|
return irq_create_mapping(pcie->rp_irq_domain, pin - 1);
|
|
|
|
else
|
|
|
|
return of_irq_parse_and_map_pci(dev, slot, pin);
|
|
|
|
}
|
|
|
|
|
2020-04-30 08:06:20 +00:00
|
|
|
static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
phy_power_off(pcie->phy);
|
|
|
|
phy_exit(pcie->phy);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_enable_phy(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!pcie->phy)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = phy_init(pcie->phy);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
|
|
|
|
if (ret) {
|
|
|
|
phy_exit(pcie->phy);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = phy_power_on(pcie->phy);
|
2020-09-02 14:43:44 +00:00
|
|
|
if (ret == -EOPNOTSUPP) {
|
|
|
|
dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n");
|
|
|
|
} else if (ret) {
|
2020-04-30 08:06:20 +00:00
|
|
|
phy_exit(pcie->phy);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int advk_pcie_setup_phy(struct advk_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct device *dev = &pcie->pdev->dev;
|
|
|
|
struct device_node *node = dev->of_node;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
pcie->phy = devm_of_phy_get(dev, node, NULL);
|
|
|
|
if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
|
|
|
|
return PTR_ERR(pcie->phy);
|
|
|
|
|
|
|
|
/* Old bindings miss the PHY handle */
|
|
|
|
if (IS_ERR(pcie->phy)) {
|
|
|
|
dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
|
|
|
|
pcie->phy = NULL;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = advk_pcie_enable_phy(pcie);
|
|
|
|
if (ret)
|
|
|
|
dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static int advk_pcie_probe(struct platform_device *pdev)
|
|
|
|
{
|
2016-10-06 18:27:46 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
2016-06-30 09:32:31 +00:00
|
|
|
struct advk_pcie *pcie;
|
2017-06-28 20:13:56 +00:00
|
|
|
struct pci_host_bridge *bridge;
|
2021-06-24 21:55:45 +00:00
|
|
|
struct resource_entry *entry;
|
2022-01-10 01:49:59 +00:00
|
|
|
int ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2017-06-28 20:13:56 +00:00
|
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
|
|
|
|
if (!bridge)
|
2016-06-30 09:32:31 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-06-28 20:13:56 +00:00
|
|
|
pcie = pci_host_bridge_priv(bridge);
|
2016-06-30 09:32:31 +00:00
|
|
|
pcie->pdev = pdev;
|
2020-09-07 11:10:37 +00:00
|
|
|
platform_set_drvdata(pdev, pcie);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
resource_list_for_each_entry(entry, &bridge->windows) {
|
|
|
|
resource_size_t start = entry->res->start;
|
|
|
|
resource_size_t size = resource_size(entry->res);
|
|
|
|
unsigned long type = resource_type(entry->res);
|
|
|
|
u64 win_size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Aardvark hardware allows to configure also PCIe window
|
|
|
|
* for config type 0 and type 1 mapping, but driver uses
|
|
|
|
* only PIO for issuing configuration transfers which does
|
|
|
|
* not use PCIe window configuration.
|
|
|
|
*/
|
2021-11-25 16:01:47 +00:00
|
|
|
if (type != IORESOURCE_MEM && type != IORESOURCE_IO)
|
2021-06-24 21:55:45 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Skip transparent memory resources. Default outbound access
|
|
|
|
* configuration is set to transparent memory access so it
|
|
|
|
* does not need window configuration.
|
|
|
|
*/
|
2021-11-25 16:01:47 +00:00
|
|
|
if (type == IORESOURCE_MEM && entry->offset == 0)
|
2021-06-24 21:55:45 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The n-th PCIe window is configured by tuple (match, remap, mask)
|
|
|
|
* and an access to address A uses this window if A matches the
|
|
|
|
* match with given mask.
|
|
|
|
* So every PCIe window size must be a power of two and every start
|
|
|
|
* address must be aligned to window size. Minimal size is 64 KiB
|
|
|
|
* because lower 16 bits of mask must be zero. Remapped address
|
|
|
|
* may have set only bits from the mask.
|
|
|
|
*/
|
|
|
|
while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
|
|
|
|
/* Calculate the largest aligned window size */
|
|
|
|
win_size = (1ULL << (fls64(size)-1)) |
|
|
|
|
(start ? (1ULL << __ffs64(start)) : 0);
|
|
|
|
win_size = 1ULL << __ffs64(win_size);
|
|
|
|
if (win_size < 0x10000)
|
|
|
|
break;
|
|
|
|
|
|
|
|
dev_dbg(dev,
|
|
|
|
"Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n",
|
|
|
|
pcie->wins_count, (unsigned long long)start,
|
|
|
|
(unsigned long long)start + win_size, type);
|
|
|
|
|
|
|
|
if (type == IORESOURCE_IO) {
|
|
|
|
pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
|
|
|
|
pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
|
|
|
|
} else {
|
|
|
|
pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
|
|
|
|
pcie->wins[pcie->wins_count].match = start;
|
|
|
|
}
|
|
|
|
pcie->wins[pcie->wins_count].remap = start - entry->offset;
|
|
|
|
pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
|
|
|
|
|
|
|
|
if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
|
|
|
|
break;
|
|
|
|
|
|
|
|
start += win_size;
|
|
|
|
size -= win_size;
|
|
|
|
pcie->wins_count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size > 0) {
|
|
|
|
dev_err(&pcie->pdev->dev,
|
|
|
|
"Invalid PCIe region [0x%llx-0x%llx]\n",
|
|
|
|
(unsigned long long)entry->res->start,
|
|
|
|
(unsigned long long)entry->res->end + 1);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-07-08 15:56:14 +00:00
|
|
|
pcie->base = devm_platform_ioremap_resource(pdev, 0);
|
2016-07-28 16:17:14 +00:00
|
|
|
if (IS_ERR(pcie->base))
|
2016-06-30 09:32:31 +00:00
|
|
|
return PTR_ERR(pcie->base);
|
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
pcie->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (pcie->irq < 0)
|
|
|
|
return pcie->irq;
|
2016-06-30 09:32:31 +00:00
|
|
|
|
2020-04-30 08:06:18 +00:00
|
|
|
pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
|
|
|
|
"reset-gpios", 0,
|
|
|
|
GPIOD_OUT_LOW,
|
|
|
|
"pcie1-reset");
|
|
|
|
ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
|
|
|
|
if (ret) {
|
|
|
|
if (ret == -ENOENT) {
|
|
|
|
pcie->reset_gpio = NULL;
|
|
|
|
} else {
|
|
|
|
if (ret != -EPROBE_DEFER)
|
|
|
|
dev_err(dev, "Failed to get reset-gpio: %i\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-30 08:06:17 +00:00
|
|
|
ret = of_pci_get_max_link_speed(dev->of_node);
|
|
|
|
if (ret <= 0 || ret > 3)
|
|
|
|
pcie->link_gen = 3;
|
|
|
|
else
|
|
|
|
pcie->link_gen = ret;
|
|
|
|
|
2020-04-30 08:06:20 +00:00
|
|
|
ret = advk_pcie_setup_phy(pcie);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_pcie_setup_hw(pcie);
|
|
|
|
|
2020-09-07 11:10:35 +00:00
|
|
|
ret = advk_sw_pci_bridge_init(pcie);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to register emulated root PCI bridge\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2018-10-18 15:37:19 +00:00
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
ret = advk_pcie_init_irq_domain(pcie);
|
|
|
|
if (ret) {
|
2016-10-06 18:27:46 +00:00
|
|
|
dev_err(dev, "Failed to initialize irq\n");
|
2016-06-30 09:32:31 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = advk_pcie_init_msi_irq_domain(pcie);
|
|
|
|
if (ret) {
|
2016-10-06 18:27:46 +00:00
|
|
|
dev_err(dev, "Failed to initialize irq\n");
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_pcie_remove_irq_domain(pcie);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:50:13 +00:00
|
|
|
ret = advk_pcie_init_rp_irq_domain(pcie);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Failed to initialize irq\n");
|
|
|
|
advk_pcie_remove_msi_irq_domain(pcie);
|
|
|
|
advk_pcie_remove_irq_domain(pcie);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);
|
|
|
|
|
2017-06-28 20:13:56 +00:00
|
|
|
bridge->sysdata = pcie;
|
|
|
|
bridge->ops = &advk_pcie_ops;
|
2022-01-10 01:50:13 +00:00
|
|
|
bridge->map_irq = advk_pcie_map_irq;
|
2017-06-28 20:13:56 +00:00
|
|
|
|
2018-06-29 09:16:20 +00:00
|
|
|
ret = pci_host_probe(bridge);
|
2017-06-28 20:13:56 +00:00
|
|
|
if (ret < 0) {
|
2022-01-10 01:49:59 +00:00
|
|
|
irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
|
2022-01-10 01:50:13 +00:00
|
|
|
advk_pcie_remove_rp_irq_domain(pcie);
|
2016-06-30 09:32:31 +00:00
|
|
|
advk_pcie_remove_msi_irq_domain(pcie);
|
|
|
|
advk_pcie_remove_irq_domain(pcie);
|
2017-06-28 20:13:56 +00:00
|
|
|
return ret;
|
2016-06-30 09:32:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-09-07 11:10:37 +00:00
|
|
|
static int advk_pcie_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct advk_pcie *pcie = platform_get_drvdata(pdev);
|
|
|
|
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
|
2021-11-30 17:29:08 +00:00
|
|
|
u32 val;
|
2021-06-24 21:55:45 +00:00
|
|
|
int i;
|
2020-09-07 11:10:37 +00:00
|
|
|
|
2021-11-30 17:29:07 +00:00
|
|
|
/* Remove PCI bus with all devices */
|
2020-09-07 11:10:37 +00:00
|
|
|
pci_lock_rescan_remove();
|
|
|
|
pci_stop_root_bus(bridge->bus);
|
|
|
|
pci_remove_root_bus(bridge->bus);
|
|
|
|
pci_unlock_rescan_remove();
|
|
|
|
|
2021-11-30 17:29:08 +00:00
|
|
|
/* Disable Root Bridge I/O space, memory space and bus mastering */
|
|
|
|
val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
|
|
advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
|
|
|
|
|
2021-11-30 17:29:09 +00:00
|
|
|
/* Disable MSI */
|
|
|
|
val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
|
|
|
|
val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
|
|
|
|
advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
|
|
|
|
|
|
|
|
/* Clear MSI address */
|
|
|
|
advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
|
|
|
|
advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
|
|
|
|
|
|
|
|
/* Mask all interrupts */
|
|
|
|
advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
|
|
|
|
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
|
|
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
|
|
|
|
advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
|
|
|
|
|
|
|
|
/* Clear all interrupts */
|
|
|
|
advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
|
|
|
|
advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
|
|
|
|
advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
|
|
|
|
advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
|
|
|
|
|
2022-01-10 01:49:59 +00:00
|
|
|
/* Remove IRQ handler */
|
|
|
|
irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
|
|
|
|
|
2021-11-30 17:29:07 +00:00
|
|
|
/* Remove IRQ domains */
|
2022-01-10 01:50:13 +00:00
|
|
|
advk_pcie_remove_rp_irq_domain(pcie);
|
2020-09-07 11:10:37 +00:00
|
|
|
advk_pcie_remove_msi_irq_domain(pcie);
|
|
|
|
advk_pcie_remove_irq_domain(pcie);
|
|
|
|
|
2021-11-30 17:29:10 +00:00
|
|
|
/* Free config space for emulated root bridge */
|
|
|
|
pci_bridge_emul_cleanup(&pcie->bridge);
|
|
|
|
|
2021-11-30 17:29:11 +00:00
|
|
|
/* Assert PERST# signal which prepares PCIe card for power down */
|
|
|
|
if (pcie->reset_gpio)
|
|
|
|
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
|
|
|
|
|
2021-11-30 17:29:12 +00:00
|
|
|
/* Disable link training */
|
|
|
|
val = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
|
|
val &= ~LINK_TRAINING_EN;
|
|
|
|
advk_writel(pcie, val, PCIE_CORE_CTRL0_REG);
|
|
|
|
|
2021-06-24 21:55:45 +00:00
|
|
|
/* Disable outbound address windows mapping */
|
|
|
|
for (i = 0; i < OB_WIN_COUNT; i++)
|
|
|
|
advk_pcie_disable_ob_win(pcie, i);
|
|
|
|
|
2021-11-30 17:29:13 +00:00
|
|
|
/* Disable phy */
|
|
|
|
advk_pcie_disable_phy(pcie);
|
|
|
|
|
2020-09-07 11:10:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-30 09:32:31 +00:00
|
|
|
static const struct of_device_id advk_pcie_of_match_table[] = {
|
|
|
|
{ .compatible = "marvell,armada-3700-pcie", },
|
|
|
|
{},
|
|
|
|
};
|
2020-09-07 11:10:37 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table);
|
2016-06-30 09:32:31 +00:00
|
|
|
|
|
|
|
static struct platform_driver advk_pcie_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "advk-pcie",
|
|
|
|
.of_match_table = advk_pcie_of_match_table,
|
|
|
|
},
|
|
|
|
.probe = advk_pcie_probe,
|
2020-09-07 11:10:37 +00:00
|
|
|
.remove = advk_pcie_remove,
|
2016-06-30 09:32:31 +00:00
|
|
|
};
|
2020-09-07 11:10:37 +00:00
|
|
|
module_platform_driver(advk_pcie_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Aardvark PCIe controller");
|
|
|
|
MODULE_LICENSE("GPL v2");
|