2012-05-09 18:37:20 +00:00
|
|
|
/*
|
|
|
|
* Copyright © 2012 Intel Corporation
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
|
|
* to deal in the Software without restriction, including without limitation
|
|
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice (including the next
|
|
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
|
|
* Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
|
|
* IN THE SOFTWARE.
|
|
|
|
*
|
|
|
|
* Authors:
|
|
|
|
* Eugeni Dodonov <eugeni.dodonov@intel.com>
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
2022-02-25 23:46:29 +00:00
|
|
|
#include <linux/string_helpers.h>
|
|
|
|
|
2022-04-21 07:31:08 +00:00
|
|
|
#include <drm/display/drm_scdc_helper.h>
|
2021-10-05 20:23:22 +00:00
|
|
|
#include <drm/drm_privacy_screen_consumer.h>
|
2019-04-05 11:00:03 +00:00
|
|
|
|
2012-05-09 18:37:20 +00:00
|
|
|
#include "i915_drv.h"
|
2022-11-09 15:35:22 +00:00
|
|
|
#include "i915_reg.h"
|
2023-06-30 15:58:46 +00:00
|
|
|
#include "icl_dsi.h"
|
2019-04-05 11:00:03 +00:00
|
|
|
#include "intel_audio.h"
|
2022-06-02 09:45:42 +00:00
|
|
|
#include "intel_audio_regs.h"
|
2021-08-25 11:06:50 +00:00
|
|
|
#include "intel_backlight.h"
|
2019-04-25 18:52:53 +00:00
|
|
|
#include "intel_combo_phy.h"
|
2022-01-11 05:15:58 +00:00
|
|
|
#include "intel_combo_phy_regs.h"
|
2019-04-05 11:00:06 +00:00
|
|
|
#include "intel_connector.h"
|
2021-04-27 12:03:15 +00:00
|
|
|
#include "intel_crtc.h"
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
#include "intel_cx0_phy.h"
|
2023-04-13 21:24:40 +00:00
|
|
|
#include "intel_cx0_phy_regs.h"
|
2019-04-05 11:00:05 +00:00
|
|
|
#include "intel_ddi.h"
|
2021-02-04 19:43:18 +00:00
|
|
|
#include "intel_ddi_buf_trans.h"
|
2021-04-30 14:39:44 +00:00
|
|
|
#include "intel_de.h"
|
2022-04-14 21:06:53 +00:00
|
|
|
#include "intel_display_power.h"
|
2019-08-06 11:39:33 +00:00
|
|
|
#include "intel_display_types.h"
|
2022-10-25 11:44:55 +00:00
|
|
|
#include "intel_dkl_phy.h"
|
2022-10-25 11:44:56 +00:00
|
|
|
#include "intel_dkl_phy_regs.h"
|
2019-04-05 11:00:17 +00:00
|
|
|
#include "intel_dp.h"
|
2023-02-16 23:13:09 +00:00
|
|
|
#include "intel_dp_aux.h"
|
2019-04-29 12:29:25 +00:00
|
|
|
#include "intel_dp_link_training.h"
|
2021-02-04 19:43:19 +00:00
|
|
|
#include "intel_dp_mst.h"
|
2019-05-02 15:02:40 +00:00
|
|
|
#include "intel_dpio_phy.h"
|
2018-11-29 14:12:17 +00:00
|
|
|
#include "intel_dsi.h"
|
2021-02-04 19:43:19 +00:00
|
|
|
#include "intel_fdi.h"
|
2019-04-29 12:29:24 +00:00
|
|
|
#include "intel_fifo_underrun.h"
|
2019-05-02 15:02:47 +00:00
|
|
|
#include "intel_gmbus.h"
|
2019-04-05 11:00:13 +00:00
|
|
|
#include "intel_hdcp.h"
|
2019-04-05 11:00:18 +00:00
|
|
|
#include "intel_hdmi.h"
|
2019-04-29 12:50:11 +00:00
|
|
|
#include "intel_hotplug.h"
|
2022-11-09 14:42:06 +00:00
|
|
|
#include "intel_hti.h"
|
2019-04-05 11:00:11 +00:00
|
|
|
#include "intel_lspcon.h"
|
2022-10-25 10:26:42 +00:00
|
|
|
#include "intel_mg_phy_regs.h"
|
2023-05-10 10:31:29 +00:00
|
|
|
#include "intel_modeset_lock.h"
|
2021-01-08 17:44:09 +00:00
|
|
|
#include "intel_pps.h"
|
2019-04-05 11:00:09 +00:00
|
|
|
#include "intel_psr.h"
|
2022-08-29 13:18:21 +00:00
|
|
|
#include "intel_quirks.h"
|
2021-07-23 17:42:33 +00:00
|
|
|
#include "intel_snps_phy.h"
|
2019-06-28 14:36:15 +00:00
|
|
|
#include "intel_tc.h"
|
2019-04-29 12:29:32 +00:00
|
|
|
#include "intel_vdsc.h"
|
2023-03-01 15:19:49 +00:00
|
|
|
#include "intel_vdsc_regs.h"
|
2021-02-05 14:48:42 +00:00
|
|
|
#include "skl_scaler.h"
|
2021-02-05 14:48:36 +00:00
|
|
|
#include "skl_universal_plane.h"
|
2012-05-09 18:37:20 +00:00
|
|
|
|
2017-02-23 17:35:06 +00:00
|
|
|
static const u8 index_to_dp_signal_levels[] = {
|
|
|
|
[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
|
|
|
|
[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
|
|
|
|
[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
|
|
|
|
[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
|
|
|
|
[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
|
|
|
|
[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
|
|
|
|
[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
|
|
|
|
[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
|
|
|
|
[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
|
|
|
|
[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
|
|
|
|
};
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
|
2021-10-01 13:01:04 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans)
|
2016-07-12 12:59:30 +00:00
|
|
|
{
|
2021-10-01 13:01:04 +00:00
|
|
|
int level;
|
2016-07-12 12:59:30 +00:00
|
|
|
|
2023-02-16 00:04:25 +00:00
|
|
|
level = intel_bios_hdmi_level_shift(encoder->devdata);
|
2020-01-17 14:29:22 +00:00
|
|
|
if (level < 0)
|
2021-10-01 13:01:04 +00:00
|
|
|
level = trans->hdmi_default_entry;
|
2017-10-18 18:19:34 +00:00
|
|
|
|
2017-10-18 18:19:58 +00:00
|
|
|
return level;
|
2016-07-12 12:59:30 +00:00
|
|
|
}
|
|
|
|
|
2021-10-01 13:00:59 +00:00
|
|
|
static bool has_buf_trans_select(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
|
|
|
|
}
|
|
|
|
|
2021-10-01 13:00:58 +00:00
|
|
|
static bool has_iboost(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
|
|
|
|
}
|
|
|
|
|
2013-11-03 04:07:41 +00:00
|
|
|
/*
|
|
|
|
* Starting with Haswell, DDI port buffers must be programmed with correct
|
2016-07-12 12:59:33 +00:00
|
|
|
* values in advance. This function programs the correct values for
|
|
|
|
* DP/eDP/FDI use cases.
|
2012-05-09 18:37:20 +00:00
|
|
|
*/
|
2021-06-08 07:35:47 +00:00
|
|
|
void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2012-05-09 18:37:20 +00:00
|
|
|
{
|
2015-12-08 17:59:44 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2015-07-10 11:10:55 +00:00
|
|
|
u32 iboost_bit = 0;
|
2017-02-23 17:35:05 +00:00
|
|
|
int i, n_entries;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2013-11-03 04:07:41 +00:00
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2021-06-08 07:35:48 +00:00
|
|
|
return;
|
2013-11-03 04:07:41 +00:00
|
|
|
|
2017-10-16 14:57:03 +00:00
|
|
|
/* If we're boosting the current, set bit 31 of trans1 */
|
2021-10-01 13:00:58 +00:00
|
|
|
if (has_iboost(dev_priv) &&
|
2023-02-16 00:04:25 +00:00
|
|
|
intel_bios_dp_boost_level(encoder->devdata))
|
2017-10-16 14:57:03 +00:00
|
|
|
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
|
2012-05-09 18:37:20 +00:00
|
|
|
|
2017-02-23 17:35:05 +00:00
|
|
|
for (i = 0; i < n_entries; i++) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
|
2021-09-27 18:24:47 +00:00
|
|
|
trans->entries[i].hsw.trans1 | iboost_bit);
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
|
2021-09-27 18:24:47 +00:00
|
|
|
trans->entries[i].hsw.trans2);
|
2012-05-09 18:37:20 +00:00
|
|
|
}
|
2016-07-12 12:59:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Starting with Haswell, DDI port buffers must be programmed with correct
|
|
|
|
* values in advance. This function programs the correct values for
|
|
|
|
* HDMI/DVI use cases.
|
|
|
|
*/
|
2021-06-08 07:35:47 +00:00
|
|
|
static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
|
2021-10-01 13:01:00 +00:00
|
|
|
const struct intel_crtc_state *crtc_state)
|
2016-07-12 12:59:33 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2021-10-01 13:01:05 +00:00
|
|
|
int level = intel_ddi_level(encoder, crtc_state, 0);
|
2016-07-12 12:59:33 +00:00
|
|
|
u32 iboost_bit = 0;
|
2017-10-18 18:19:58 +00:00
|
|
|
int n_entries;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2014-08-01 10:07:54 +00:00
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2017-10-18 18:19:34 +00:00
|
|
|
return;
|
|
|
|
|
2017-10-16 14:56:57 +00:00
|
|
|
/* If we're boosting the current, set bit 31 of trans1 */
|
2021-10-01 13:00:58 +00:00
|
|
|
if (has_iboost(dev_priv) &&
|
2023-02-16 00:04:25 +00:00
|
|
|
intel_bios_hdmi_boost_level(encoder->devdata))
|
2017-10-16 14:56:57 +00:00
|
|
|
iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2013-09-12 20:06:24 +00:00
|
|
|
/* Entry 9 is for HDMI: */
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
|
2021-09-27 18:24:47 +00:00
|
|
|
trans->entries[level].hsw.trans1 | iboost_bit);
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
|
2021-09-27 18:24:47 +00:00
|
|
|
trans->entries[level].hsw.trans2);
|
2012-05-09 18:37:20 +00:00
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* FIXME: find out why Bspec's 100us timeout is too short */
|
|
|
|
ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
|
|
|
|
XELPDP_PORT_BUF_PHY_IDLE), 10000);
|
|
|
|
if (ret)
|
|
|
|
drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
|
|
|
|
2021-02-04 19:43:19 +00:00
|
|
|
void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
2012-11-29 13:29:31 +00:00
|
|
|
{
|
2020-07-01 22:10:51 +00:00
|
|
|
if (IS_BROXTON(dev_priv)) {
|
|
|
|
udelay(16);
|
|
|
|
return;
|
2012-11-29 13:29:31 +00:00
|
|
|
}
|
2020-07-01 22:10:51 +00:00
|
|
|
|
|
|
|
if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
|
|
|
|
DDI_BUF_IS_IDLE), 8))
|
|
|
|
drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
|
|
|
|
port_name(port));
|
2012-11-29 13:29:31 +00:00
|
|
|
}
|
2012-05-09 18:37:21 +00:00
|
|
|
|
2020-07-01 22:10:52 +00:00
|
|
|
static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
2022-12-07 14:54:36 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, port);
|
|
|
|
int timeout_us;
|
2021-07-23 17:42:35 +00:00
|
|
|
int ret;
|
|
|
|
|
2020-07-01 22:10:52 +00:00
|
|
|
/* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
|
2021-04-12 05:46:07 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) < 10) {
|
2020-07-01 22:10:52 +00:00
|
|
|
usleep_range(518, 1000);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14) {
|
|
|
|
timeout_us = 10000;
|
|
|
|
} else if (IS_DG2(dev_priv)) {
|
2022-12-07 14:54:36 +00:00
|
|
|
timeout_us = 1200;
|
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 12) {
|
|
|
|
if (intel_phy_is_tc(dev_priv, phy))
|
|
|
|
timeout_us = 3000;
|
|
|
|
else
|
|
|
|
timeout_us = 1000;
|
|
|
|
} else {
|
|
|
|
timeout_us = 500;
|
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
|
|
|
|
timeout_us, 10, 10);
|
|
|
|
else
|
|
|
|
ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
|
|
|
|
timeout_us, 10, 10);
|
2021-07-23 17:42:35 +00:00
|
|
|
|
|
|
|
if (ret)
|
2020-07-01 22:10:52 +00:00
|
|
|
drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:20 +00:00
|
|
|
static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
|
2016-09-01 22:08:07 +00:00
|
|
|
{
|
2018-03-20 22:06:35 +00:00
|
|
|
switch (pll->info->id) {
|
2016-09-01 22:08:07 +00:00
|
|
|
case DPLL_ID_WRPLL1:
|
|
|
|
return PORT_CLK_SEL_WRPLL1;
|
|
|
|
case DPLL_ID_WRPLL2:
|
|
|
|
return PORT_CLK_SEL_WRPLL2;
|
|
|
|
case DPLL_ID_SPLL:
|
|
|
|
return PORT_CLK_SEL_SPLL;
|
|
|
|
case DPLL_ID_LCPLL_810:
|
|
|
|
return PORT_CLK_SEL_LCPLL_810;
|
|
|
|
case DPLL_ID_LCPLL_1350:
|
|
|
|
return PORT_CLK_SEL_LCPLL_1350;
|
|
|
|
case DPLL_ID_LCPLL_2700:
|
|
|
|
return PORT_CLK_SEL_LCPLL_2700;
|
|
|
|
default:
|
2018-03-20 22:06:35 +00:00
|
|
|
MISSING_CASE(pll->info->id);
|
2016-09-01 22:08:07 +00:00
|
|
|
return PORT_CLK_SEL_NONE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-01-25 22:24:43 +00:00
|
|
|
static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
|
2019-01-18 12:01:21 +00:00
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-04-27 23:14:36 +00:00
|
|
|
{
|
2018-10-04 09:46:00 +00:00
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
int clock = crtc_state->port_clock;
|
2018-04-27 23:14:36 +00:00
|
|
|
const enum intel_dpll_id id = pll->info->id;
|
|
|
|
|
|
|
|
switch (id) {
|
|
|
|
default:
|
2019-01-25 22:24:43 +00:00
|
|
|
/*
|
|
|
|
* DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
|
|
|
|
* here, so do warn if this get passed in
|
|
|
|
*/
|
2018-04-27 23:14:36 +00:00
|
|
|
MISSING_CASE(id);
|
|
|
|
return DDI_CLK_SEL_NONE;
|
2018-05-22 00:25:48 +00:00
|
|
|
case DPLL_ID_ICL_TBTPLL:
|
|
|
|
switch (clock) {
|
|
|
|
case 162000:
|
|
|
|
return DDI_CLK_SEL_TBT_162;
|
|
|
|
case 270000:
|
|
|
|
return DDI_CLK_SEL_TBT_270;
|
|
|
|
case 540000:
|
|
|
|
return DDI_CLK_SEL_TBT_540;
|
|
|
|
case 810000:
|
|
|
|
return DDI_CLK_SEL_TBT_810;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(clock);
|
2019-01-25 22:24:42 +00:00
|
|
|
return DDI_CLK_SEL_NONE;
|
2018-05-22 00:25:48 +00:00
|
|
|
}
|
2018-04-27 23:14:36 +00:00
|
|
|
case DPLL_ID_ICL_MGPLL1:
|
|
|
|
case DPLL_ID_ICL_MGPLL2:
|
|
|
|
case DPLL_ID_ICL_MGPLL3:
|
|
|
|
case DPLL_ID_ICL_MGPLL4:
|
2019-09-24 21:00:40 +00:00
|
|
|
case DPLL_ID_TGL_MGPLL5:
|
|
|
|
case DPLL_ID_TGL_MGPLL6:
|
2018-04-27 23:14:36 +00:00
|
|
|
return DDI_CLK_SEL_MG;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-19 00:06:23 +00:00
|
|
|
static u32 ddi_buf_phy_link_rate(int port_clock)
|
|
|
|
{
|
|
|
|
switch (port_clock) {
|
|
|
|
case 162000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(0);
|
|
|
|
case 216000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(4);
|
|
|
|
case 243000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(5);
|
|
|
|
case 270000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(1);
|
|
|
|
case 324000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(6);
|
|
|
|
case 432000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(7);
|
|
|
|
case 540000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(2);
|
|
|
|
case 810000:
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(3);
|
|
|
|
default:
|
|
|
|
MISSING_CASE(port_clock);
|
|
|
|
return DDI_BUF_PHY_LINK_RATE(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2014-05-02 03:36:43 +00:00
|
|
|
{
|
2021-05-19 00:06:13 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2020-07-01 04:50:54 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2021-05-19 00:06:13 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2014-05-02 03:36:43 +00:00
|
|
|
|
2021-09-30 13:43:08 +00:00
|
|
|
/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
|
2020-07-01 04:50:54 +00:00
|
|
|
intel_dp->DP = dig_port->saved_port_bits |
|
2021-09-30 13:43:08 +00:00
|
|
|
DDI_PORT_WIDTH(crtc_state->lane_count) |
|
|
|
|
DDI_BUF_TRANS_SELECT(0);
|
2021-05-19 00:06:13 +00:00
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
if (DISPLAY_VER(i915) >= 14) {
|
|
|
|
if (intel_dp_is_uhbr(crtc_state))
|
|
|
|
intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
|
|
|
|
else
|
|
|
|
intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
|
|
|
|
}
|
|
|
|
|
2021-05-19 00:06:23 +00:00
|
|
|
if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
|
|
|
|
intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
|
2021-09-21 00:23:05 +00:00
|
|
|
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
|
2021-05-19 00:06:23 +00:00
|
|
|
intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
|
|
|
|
}
|
2014-05-02 03:36:43 +00:00
|
|
|
}
|
|
|
|
|
2018-08-17 21:52:09 +00:00
|
|
|
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
|
2018-08-17 21:52:09 +00:00
|
|
|
|
|
|
|
switch (val) {
|
|
|
|
case DDI_CLK_SEL_NONE:
|
|
|
|
return 0;
|
|
|
|
case DDI_CLK_SEL_TBT_162:
|
|
|
|
return 162000;
|
|
|
|
case DDI_CLK_SEL_TBT_270:
|
|
|
|
return 270000;
|
|
|
|
case DDI_CLK_SEL_TBT_540:
|
|
|
|
return 540000;
|
|
|
|
case DDI_CLK_SEL_TBT_810:
|
|
|
|
return 810000;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(val);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-05-04 12:33:50 +00:00
|
|
|
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
|
|
|
/* CRT dotclock is determined via other means */
|
|
|
|
if (pipe_config->has_pch_encoder)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pipe_config->hw.adjusted_mode.crtc_clock =
|
|
|
|
intel_crtc_dotclock(pipe_config);
|
2015-06-30 12:33:51 +00:00
|
|
|
}
|
2014-11-13 14:55:16 +00:00
|
|
|
|
2019-09-19 19:53:05 +00:00
|
|
|
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-10-15 18:51:30 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2017-03-02 12:58:55 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2017-03-02 12:58:56 +00:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2017-10-19 13:37:12 +00:00
|
|
|
u32 temp;
|
2012-10-15 18:51:30 +00:00
|
|
|
|
2017-10-19 13:37:12 +00:00
|
|
|
if (!intel_crtc_has_dp_encoder(crtc_state))
|
|
|
|
return;
|
2016-03-18 15:05:42 +00:00
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
|
2017-10-19 13:37:12 +00:00
|
|
|
|
2019-07-18 14:50:47 +00:00
|
|
|
temp = DP_MSA_MISC_SYNC_CLOCK;
|
drm/i915: set DP Main Stream Attribute for color range on DDI platforms
Since Haswell we have no color range indication either in the pipe or
port registers for DP. Instead, there's a separate register for setting
the DP Main Stream Attributes (MSA) directly. The MSA register
definition makes no references to colorimetry, just a vague reference to
the DP spec. The connection to the color range was lost.
Apparently we've failed to set the proper MSA bit for limited, or CEA,
range ever since the first DDI platforms. We've started setting other
MSA parameters since commit dae847991a43 ("drm/i915: add
intel_ddi_set_pipe_settings").
Without the crucial bit of information, the DP sink has no way of
knowing the source is actually transmitting limited range RGB, leading
to "washed out" colors. With the colorimetry information, compliant
sinks should be able to handle the limited range properly. Native
(i.e. non-LSPCON) HDMI was not affected because we do pass the color
range via AVI infoframes.
Though not the root cause, the problem was made worse for DDI platforms
with commit 55bc60db5988 ("drm/i915: Add "Automatic" mode for the
"Broadcast RGB" property"), which selects limited range RGB
automatically based on the mode, as per the DP, HDMI and CEA specs.
After all these years, the fix boils down to flipping one bit.
[Per testing reports, this fixes DP sinks, but not the LSPCON. My
educated guess is that the LSPCON fails to turn the CEA range MSA into
AVI infoframes for HDMI.]
Reported-by: Michał Kopeć <mkopec12@gmail.com>
Reported-by: N. W. <nw9165-3201@yahoo.com>
Reported-by: Nicholas Stommel <nicholas.stommel@gmail.com>
Reported-by: Tom Yan <tom.ty89@gmail.com>
Tested-by: Nicholas Stommel <nicholas.stommel@gmail.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=100023
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107476
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=94921
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: <stable@vger.kernel.org> # v3.9+
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180814060001.18224-1-jani.nikula@intel.com
2018-08-14 06:00:01 +00:00
|
|
|
|
2017-10-19 13:37:12 +00:00
|
|
|
switch (crtc_state->pipe_bpp) {
|
|
|
|
case 18:
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_6_BPC;
|
2017-10-19 13:37:12 +00:00
|
|
|
break;
|
|
|
|
case 24:
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_8_BPC;
|
2017-10-19 13:37:12 +00:00
|
|
|
break;
|
|
|
|
case 30:
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_10_BPC;
|
2017-10-19 13:37:12 +00:00
|
|
|
break;
|
|
|
|
case 36:
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_12_BPC;
|
2017-10-19 13:37:12 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(crtc_state->pipe_bpp);
|
|
|
|
break;
|
2012-10-15 18:51:30 +00:00
|
|
|
}
|
2017-10-19 13:37:12 +00:00
|
|
|
|
2019-07-18 16:45:23 +00:00
|
|
|
/* nonsense combination */
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
|
|
|
|
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
|
2019-07-18 16:45:23 +00:00
|
|
|
|
|
|
|
if (crtc_state->limited_color_range)
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_COLOR_CEA_RGB;
|
2019-07-18 16:45:23 +00:00
|
|
|
|
2018-10-12 06:23:14 +00:00
|
|
|
/*
|
|
|
|
* As per DP 1.2 spec section 2.3.4.3 while sending
|
|
|
|
* YCBCR 444 signals we should program MSA MISC1/0 fields with
|
2019-07-18 14:50:43 +00:00
|
|
|
* colorspace information.
|
2018-10-12 06:23:14 +00:00
|
|
|
*/
|
|
|
|
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
|
2019-07-18 14:50:43 +00:00
|
|
|
|
2019-05-21 12:17:19 +00:00
|
|
|
/*
|
|
|
|
* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
|
|
|
|
* of Color Encoding Format and Content Color Gamut] while sending
|
2019-09-19 19:53:05 +00:00
|
|
|
* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
|
|
|
|
* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
|
2019-05-21 12:17:19 +00:00
|
|
|
*/
|
2019-11-06 21:26:36 +00:00
|
|
|
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
|
2019-07-18 14:50:47 +00:00
|
|
|
temp |= DP_MSA_MISC_COLOR_VSC_SDP;
|
2019-09-19 19:53:05 +00:00
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
|
2012-10-15 18:51:30 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
|
|
|
|
{
|
|
|
|
if (master_transcoder == TRANSCODER_EDP)
|
|
|
|
return 0;
|
|
|
|
else
|
|
|
|
return master_transcoder + 1;
|
|
|
|
}
|
|
|
|
|
2021-09-09 12:52:01 +00:00
|
|
|
static void
|
|
|
|
intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
if (intel_dp_is_uhbr(crtc_state))
|
|
|
|
val = TRANS_DP2_128B132B_CHANNEL_CODING;
|
|
|
|
|
|
|
|
intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
|
|
|
|
}
|
|
|
|
|
2019-08-23 08:20:47 +00:00
|
|
|
/*
|
|
|
|
* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
|
|
|
|
*
|
|
|
|
* Only intended to be used by intel_ddi_enable_transcoder_func() and
|
|
|
|
* intel_ddi_config_transcoder_func().
|
|
|
|
*/
|
|
|
|
static u32
|
2020-04-17 13:47:20 +00:00
|
|
|
intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2012-10-05 15:05:53 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2017-03-02 12:58:55 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
enum pipe pipe = crtc->pipe;
|
2017-03-02 12:58:56 +00:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2019-01-18 12:01:21 +00:00
|
|
|
u32 temp;
|
2012-10-05 15:05:53 +00:00
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
|
|
|
|
temp = TRANS_DDI_FUNC_ENABLE;
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2019-07-13 01:09:20 +00:00
|
|
|
temp |= TGL_TRANS_DDI_SELECT_PORT(port);
|
|
|
|
else
|
|
|
|
temp |= TRANS_DDI_SELECT_PORT(port);
|
2012-08-08 17:15:29 +00:00
|
|
|
|
2017-03-02 12:58:56 +00:00
|
|
|
switch (crtc_state->pipe_bpp) {
|
2022-05-31 16:25:27 +00:00
|
|
|
default:
|
|
|
|
MISSING_CASE(crtc_state->pipe_bpp);
|
|
|
|
fallthrough;
|
2012-08-08 17:15:29 +00:00
|
|
|
case 18:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_6;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 24:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_8;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 30:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_10;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
case 36:
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_BPC_12;
|
2012-08-08 17:15:29 +00:00
|
|
|
break;
|
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2019-10-31 11:26:02 +00:00
|
|
|
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_PVSYNC;
|
2019-10-31 11:26:02 +00:00
|
|
|
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_PHSYNC;
|
2012-08-08 17:15:28 +00:00
|
|
|
|
2012-10-23 20:30:04 +00:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP) {
|
|
|
|
switch (pipe) {
|
2022-05-31 16:25:27 +00:00
|
|
|
default:
|
|
|
|
MISSING_CASE(pipe);
|
|
|
|
fallthrough;
|
2012-10-23 20:30:04 +00:00
|
|
|
case PIPE_A:
|
2013-11-03 04:07:37 +00:00
|
|
|
/* On Haswell, can only use the always-on power well for
|
|
|
|
* eDP when not using the panel fitter, and when not
|
|
|
|
* using motion blur mitigation (which we don't
|
|
|
|
* support). */
|
2019-04-25 16:29:06 +00:00
|
|
|
if (crtc_state->pch_pfit.force_thru)
|
2013-01-29 18:35:20 +00:00
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
|
|
|
|
else
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ON;
|
2012-10-23 20:30:04 +00:00
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
|
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-19 13:37:15 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
2017-03-02 12:58:56 +00:00
|
|
|
if (crtc_state->has_hdmi_sink)
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_HDMI;
|
2012-10-05 15:05:53 +00:00
|
|
|
else
|
2012-10-24 18:06:19 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DVI;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 11:24:03 +00:00
|
|
|
|
|
|
|
if (crtc_state->hdmi_scrambling)
|
2018-12-10 22:52:54 +00:00
|
|
|
temp |= TRANS_DDI_HDMI_SCRAMBLING;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 11:24:03 +00:00
|
|
|
if (crtc_state->hdmi_high_tmds_clock_ratio)
|
|
|
|
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
|
2023-04-13 21:24:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
|
2017-10-19 13:37:15 +00:00
|
|
|
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
|
2021-09-09 12:51:57 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
|
2017-03-02 12:58:56 +00:00
|
|
|
temp |= (crtc_state->fdi_lanes - 1) << 1;
|
2017-10-19 13:37:15 +00:00
|
|
|
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
|
2021-09-09 12:52:03 +00:00
|
|
|
if (intel_dp_is_uhbr(crtc_state))
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
|
|
|
|
else
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_MST;
|
2017-03-02 12:58:56 +00:00
|
|
|
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
|
2019-10-29 03:50:49 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2019-12-23 01:06:49 +00:00
|
|
|
enum transcoder master;
|
|
|
|
|
|
|
|
master = crtc_state->mst_master_transcoder;
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm,
|
|
|
|
master == INVALID_TRANSCODER);
|
2019-12-23 01:06:49 +00:00
|
|
|
temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
|
|
|
|
}
|
2012-10-05 15:05:53 +00:00
|
|
|
} else {
|
2017-10-19 13:37:15 +00:00
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
|
|
|
temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
|
2012-10-05 15:05:53 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
|
2020-03-13 16:48:26 +00:00
|
|
|
crtc_state->master_transcoder != INVALID_TRANSCODER) {
|
|
|
|
u8 master_select =
|
|
|
|
bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
|
|
|
|
|
|
|
|
temp |= TRANS_DDI_PORT_SYNC_ENABLE |
|
|
|
|
TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
|
|
|
|
}
|
|
|
|
|
2019-08-23 08:20:47 +00:00
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
2020-04-17 13:47:20 +00:00
|
|
|
void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2019-08-23 08:20:47 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2019-08-23 08:20:47 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2020-03-13 16:48:20 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11) {
|
2020-03-13 16:48:20 +00:00
|
|
|
enum transcoder master_transcoder = crtc_state->master_transcoder;
|
|
|
|
u32 ctl2 = 0;
|
|
|
|
|
|
|
|
if (master_transcoder != INVALID_TRANSCODER) {
|
2020-03-13 16:48:26 +00:00
|
|
|
u8 master_select =
|
|
|
|
bdw_trans_port_sync_master_select(master_transcoder);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2020-03-13 16:48:20 +00:00
|
|
|
ctl2 |= PORT_SYNC_MODE_ENABLE |
|
2020-03-13 16:48:23 +00:00
|
|
|
PORT_SYNC_MODE_MASTER_SELECT(master_select);
|
2020-03-13 16:48:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
intel_de_write(dev_priv,
|
|
|
|
TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
|
|
|
|
}
|
|
|
|
|
2020-06-23 08:24:11 +00:00
|
|
|
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
|
|
|
|
intel_ddi_transcoder_func_reg_val_get(encoder,
|
|
|
|
crtc_state));
|
2019-08-23 08:20:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
|
|
|
|
* bit.
|
|
|
|
*/
|
|
|
|
static void
|
2020-04-17 13:47:20 +00:00
|
|
|
intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2019-08-23 08:20:47 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2019-08-23 08:20:47 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2020-03-13 16:48:20 +00:00
|
|
|
u32 ctl;
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2020-04-17 13:47:20 +00:00
|
|
|
ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
|
2020-03-13 16:48:20 +00:00
|
|
|
ctl &= ~TRANS_DDI_FUNC_ENABLE;
|
|
|
|
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
|
2012-10-05 15:05:53 +00:00
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2018-07-10 20:02:05 +00:00
|
|
|
void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
|
2012-10-05 15:05:53 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2018-07-10 20:02:05 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2020-03-13 16:48:20 +00:00
|
|
|
u32 ctl;
|
2019-12-23 01:06:51 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11)
|
2020-03-13 16:48:20 +00:00
|
|
|
intel_de_write(dev_priv,
|
|
|
|
TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
|
|
|
|
|
|
|
|
ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
2020-03-13 16:48:26 +00:00
|
|
|
|
2020-08-18 15:38:51 +00:00
|
|
|
drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
|
|
|
|
|
2020-03-13 16:48:20 +00:00
|
|
|
ctl &= ~TRANS_DDI_FUNC_ENABLE;
|
2012-10-05 15:05:53 +00:00
|
|
|
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
if (IS_DISPLAY_VER(dev_priv, 8, 10))
|
2020-03-13 16:48:26 +00:00
|
|
|
ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
|
|
|
|
TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2020-02-03 22:55:49 +00:00
|
|
|
if (!intel_dp_mst_is_master_trans(crtc_state)) {
|
2020-03-13 16:48:20 +00:00
|
|
|
ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
|
2020-02-03 22:55:49 +00:00
|
|
|
TRANS_DDI_MODE_SELECT_MASK);
|
|
|
|
}
|
2019-07-13 01:09:20 +00:00
|
|
|
} else {
|
2020-03-13 16:48:20 +00:00
|
|
|
ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
|
2019-07-13 01:09:20 +00:00
|
|
|
}
|
2020-03-13 16:48:26 +00:00
|
|
|
|
2020-03-13 16:48:20 +00:00
|
|
|
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
|
2018-07-10 20:02:05 +00:00
|
|
|
|
2022-08-29 13:18:21 +00:00
|
|
|
if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
|
2018-07-10 20:02:05 +00:00
|
|
|
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Quirk Increase DDI disabled time\n");
|
2018-07-10 20:02:05 +00:00
|
|
|
/* Quirk time at 100ms for reliable operation */
|
|
|
|
msleep(100);
|
|
|
|
}
|
2012-05-09 18:37:31 +00:00
|
|
|
}
|
|
|
|
|
2021-01-11 08:11:08 +00:00
|
|
|
int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
|
|
|
|
enum transcoder cpu_transcoder,
|
|
|
|
bool enable, u32 hdcp_mask)
|
2018-01-08 19:55:42 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_wakeref_t wakeref;
|
2018-01-08 19:55:42 +00:00
|
|
|
int ret = 0;
|
|
|
|
|
2019-01-14 14:21:24 +00:00
|
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
intel_encoder->power_domain);
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
if (drm_WARN_ON(dev, !wakeref))
|
2018-01-08 19:55:42 +00:00
|
|
|
return -ENXIO;
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
|
|
|
|
hdcp_mask, enable ? hdcp_mask : 0);
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
|
2018-01-08 19:55:42 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-10-26 21:05:51 +00:00
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_connector->base.dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2019-12-04 18:05:45 +00:00
|
|
|
struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
|
2012-10-26 21:05:51 +00:00
|
|
|
int type = intel_connector->base.connector_type;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2012-10-26 21:05:51 +00:00
|
|
|
enum transcoder cpu_transcoder;
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_wakeref_t wakeref;
|
|
|
|
enum pipe pipe = 0;
|
2019-01-18 12:01:21 +00:00
|
|
|
u32 tmp;
|
2016-02-12 16:55:16 +00:00
|
|
|
bool ret;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
2019-01-14 14:21:24 +00:00
|
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
encoder->power_domain);
|
|
|
|
if (!wakeref)
|
2014-04-01 17:55:12 +00:00
|
|
|
return false;
|
|
|
|
|
2017-03-09 13:43:41 +00:00
|
|
|
if (!encoder->get_hw_state(encoder, &pipe)) {
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
goto out;
|
|
|
|
}
|
2012-10-26 21:05:51 +00:00
|
|
|
|
2020-03-18 17:02:35 +00:00
|
|
|
if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
|
2012-10-26 21:05:51 +00:00
|
|
|
cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
else
|
2012-11-29 21:18:51 +00:00
|
|
|
cpu_transcoder = (enum transcoder) pipe;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = type == DRM_MODE_CONNECTOR_HDMIA;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = type == DRM_MODE_CONNECTOR_eDP ||
|
|
|
|
type == DRM_MODE_CONNECTOR_DisplayPort;
|
|
|
|
break;
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
|
|
|
/* if the transcoder is in MST state then
|
|
|
|
* connector isn't connected */
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
2021-09-09 12:51:57 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
|
2021-09-09 12:52:03 +00:00
|
|
|
if (HAS_DP20(dev_priv))
|
|
|
|
/* 128b/132b */
|
|
|
|
ret = false;
|
|
|
|
else
|
|
|
|
/* FDI */
|
|
|
|
ret = type == DRM_MODE_CONNECTOR_VGA;
|
2016-02-12 16:55:16 +00:00
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
|
|
|
|
default:
|
2016-02-12 16:55:16 +00:00
|
|
|
ret = false;
|
|
|
|
break;
|
2012-10-26 21:05:51 +00:00
|
|
|
}
|
2016-02-12 16:55:16 +00:00
|
|
|
|
|
|
|
out:
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
|
2016-02-12 16:55:16 +00:00
|
|
|
|
|
|
|
return ret;
|
2012-10-26 21:05:51 +00:00
|
|
|
}
|
|
|
|
|
2018-11-07 20:08:35 +00:00
|
|
|
static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
|
|
|
|
u8 *pipe_mask, bool *is_dp_mst)
|
2012-07-02 11:27:29 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_wakeref_t wakeref;
|
2017-11-09 08:37:50 +00:00
|
|
|
enum pipe p;
|
2012-07-02 11:27:29 +00:00
|
|
|
u32 tmp;
|
2018-11-07 20:08:35 +00:00
|
|
|
u8 mst_pipe_mask;
|
|
|
|
|
|
|
|
*pipe_mask = 0;
|
|
|
|
*is_dp_mst = false;
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2019-01-14 14:21:24 +00:00
|
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
encoder->power_domain);
|
|
|
|
if (!wakeref)
|
2018-11-07 20:08:35 +00:00
|
|
|
return;
|
2016-02-12 16:55:16 +00:00
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
|
2012-07-02 11:27:29 +00:00
|
|
|
if (!(tmp & DDI_BUF_CTL_ENABLE))
|
2016-02-12 16:55:16 +00:00
|
|
|
goto out;
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2020-03-18 17:02:35 +00:00
|
|
|
if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv,
|
|
|
|
TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2012-10-24 18:06:19 +00:00
|
|
|
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
|
2018-11-07 20:08:35 +00:00
|
|
|
default:
|
|
|
|
MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
|
2020-08-23 22:36:59 +00:00
|
|
|
fallthrough;
|
2012-10-24 18:06:19 +00:00
|
|
|
case TRANS_DDI_EDP_INPUT_A_ON:
|
|
|
|
case TRANS_DDI_EDP_INPUT_A_ONOFF:
|
2018-11-07 20:08:35 +00:00
|
|
|
*pipe_mask = BIT(PIPE_A);
|
2012-10-24 18:06:19 +00:00
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_B_ONOFF:
|
2018-11-07 20:08:35 +00:00
|
|
|
*pipe_mask = BIT(PIPE_B);
|
2012-10-24 18:06:19 +00:00
|
|
|
break;
|
|
|
|
case TRANS_DDI_EDP_INPUT_C_ONOFF:
|
2018-11-07 20:08:35 +00:00
|
|
|
*pipe_mask = BIT(PIPE_C);
|
2012-10-24 18:06:19 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
goto out;
|
|
|
|
}
|
2014-05-02 04:02:48 +00:00
|
|
|
|
2018-11-07 20:08:35 +00:00
|
|
|
mst_pipe_mask = 0;
|
2017-11-09 08:37:50 +00:00
|
|
|
for_each_pipe(dev_priv, p) {
|
2018-11-07 20:08:35 +00:00
|
|
|
enum transcoder cpu_transcoder = (enum transcoder)p;
|
2019-07-13 01:09:20 +00:00
|
|
|
unsigned int port_mask, ddi_select;
|
2019-08-08 00:49:34 +00:00
|
|
|
intel_wakeref_t trans_wakeref;
|
|
|
|
|
|
|
|
trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
POWER_DOMAIN_TRANSCODER(cpu_transcoder));
|
|
|
|
if (!trans_wakeref)
|
|
|
|
continue;
|
2019-07-13 01:09:20 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2019-07-13 01:09:20 +00:00
|
|
|
port_mask = TGL_TRANS_DDI_PORT_MASK;
|
|
|
|
ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
|
|
|
|
} else {
|
|
|
|
port_mask = TRANS_DDI_PORT_MASK;
|
|
|
|
ddi_select = TRANS_DDI_SELECT_PORT(port);
|
|
|
|
}
|
2017-11-09 08:37:50 +00:00
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv,
|
|
|
|
TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
2019-08-08 00:49:34 +00:00
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
|
|
|
|
trans_wakeref);
|
2016-02-12 16:55:16 +00:00
|
|
|
|
2019-07-13 01:09:20 +00:00
|
|
|
if ((tmp & port_mask) != ddi_select)
|
2018-11-07 20:08:35 +00:00
|
|
|
continue;
|
2016-02-12 16:55:16 +00:00
|
|
|
|
2021-09-09 12:52:03 +00:00
|
|
|
if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
|
|
|
|
(HAS_DP20(dev_priv) &&
|
|
|
|
(tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
|
2018-11-07 20:08:35 +00:00
|
|
|
mst_pipe_mask |= BIT(p);
|
2016-02-12 16:55:16 +00:00
|
|
|
|
2018-11-07 20:08:35 +00:00
|
|
|
*pipe_mask |= BIT(p);
|
2012-07-02 11:27:29 +00:00
|
|
|
}
|
|
|
|
|
2018-11-07 20:08:35 +00:00
|
|
|
if (!*pipe_mask)
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"No pipe for [ENCODER:%d:%s] found\n",
|
|
|
|
encoder->base.base.id, encoder->base.name);
|
2018-11-07 20:08:35 +00:00
|
|
|
|
|
|
|
if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
|
|
|
|
encoder->base.base.id, encoder->base.name,
|
|
|
|
*pipe_mask);
|
2018-11-07 20:08:35 +00:00
|
|
|
*pipe_mask = BIT(ffs(*pipe_mask) - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
|
|
|
|
encoder->base.base.id, encoder->base.name,
|
|
|
|
*pipe_mask, mst_pipe_mask);
|
2018-11-07 20:08:35 +00:00
|
|
|
else
|
|
|
|
*is_dp_mst = mst_pipe_mask;
|
2012-07-02 11:27:29 +00:00
|
|
|
|
2016-02-12 16:55:16 +00:00
|
|
|
out:
|
2021-04-07 20:39:45 +00:00
|
|
|
if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
|
2017-10-02 13:53:07 +00:00
|
|
|
if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
|
|
|
|
BXT_PHY_LANE_POWERDOWN_ACK |
|
2016-06-13 13:44:37 +00:00
|
|
|
BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_err(&dev_priv->drm,
|
|
|
|
"[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
|
|
|
|
encoder->base.base.id, encoder->base.name, tmp);
|
2016-06-13 13:44:37 +00:00
|
|
|
}
|
|
|
|
|
2019-01-14 14:21:24 +00:00
|
|
|
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
|
2018-11-07 20:08:35 +00:00
|
|
|
}
|
2016-02-12 16:55:16 +00:00
|
|
|
|
2018-11-07 20:08:35 +00:00
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
|
|
|
{
|
|
|
|
u8 pipe_mask;
|
|
|
|
bool is_mst;
|
|
|
|
|
|
|
|
intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
|
|
|
|
|
|
|
|
if (is_mst || !pipe_mask)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
*pipe = ffs(pipe_mask) - 1;
|
|
|
|
|
|
|
|
return true;
|
2012-07-02 11:27:29 +00:00
|
|
|
}
|
|
|
|
|
2020-04-20 14:04:38 +00:00
|
|
|
static enum intel_display_power_domain
|
2022-11-14 12:22:50 +00:00
|
|
|
intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-06-21 18:44:49 +00:00
|
|
|
{
|
2022-11-14 12:22:47 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
2022-11-14 12:22:50 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
|
2022-11-14 12:22:47 +00:00
|
|
|
|
2022-11-14 12:22:50 +00:00
|
|
|
/*
|
|
|
|
* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
|
2018-06-21 18:44:49 +00:00
|
|
|
* DC states enabled at the same time, while for driver initiated AUX
|
|
|
|
* transfers we need the same AUX IOs to be powered but with DC states
|
2022-11-14 12:22:50 +00:00
|
|
|
* disabled. Accordingly use the AUX_IO_<port> power domain here which
|
|
|
|
* leaves DC states enabled.
|
|
|
|
*
|
|
|
|
* Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
|
|
|
|
* AUX IO to be enabled, but all these require DC_OFF to be enabled as
|
|
|
|
* well, so we can acquire a wider AUX_<port> power domain reference
|
|
|
|
* instead of a specific AUX_IO_<port> reference without powering up any
|
|
|
|
* extra wells.
|
2018-06-21 18:44:49 +00:00
|
|
|
*/
|
2022-11-14 12:22:47 +00:00
|
|
|
if (intel_encoder_can_psr(&dig_port->base))
|
|
|
|
return intel_display_power_aux_io_domain(i915, dig_port->aux_ch);
|
2022-11-14 12:22:51 +00:00
|
|
|
else if (DISPLAY_VER(i915) < 14 &&
|
|
|
|
(intel_crtc_has_dp_encoder(crtc_state) ||
|
|
|
|
intel_phy_is_tc(i915, phy)))
|
2022-11-14 12:22:46 +00:00
|
|
|
return intel_aux_power_domain(dig_port);
|
2022-11-14 12:22:50 +00:00
|
|
|
else
|
|
|
|
return POWER_DOMAIN_INVALID;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
|
|
|
enum intel_display_power_domain domain =
|
|
|
|
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
|
|
|
|
|
|
|
|
drm_WARN_ON(&i915->drm, dig_port->aux_wakeref);
|
|
|
|
|
|
|
|
if (domain == POWER_DOMAIN_INVALID)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dig_port->aux_wakeref = intel_display_power_get(i915, domain);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
|
|
|
enum intel_display_power_domain domain =
|
|
|
|
intel_ddi_main_link_aux_domain(dig_port, crtc_state);
|
|
|
|
intel_wakeref_t wf;
|
|
|
|
|
|
|
|
wf = fetch_and_zero(&dig_port->aux_wakeref);
|
|
|
|
if (!wf)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_display_power_put(i915, domain, wf);
|
2018-06-21 18:44:49 +00:00
|
|
|
}
|
|
|
|
|
2019-04-07 12:46:55 +00:00
|
|
|
static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
2017-02-24 14:19:59 +00:00
|
|
|
{
|
2018-11-01 14:04:25 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2018-07-05 12:26:54 +00:00
|
|
|
struct intel_digital_port *dig_port;
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2018-06-21 18:44:49 +00:00
|
|
|
/*
|
|
|
|
* TODO: Add support for MST encoders. Atm, the following should never
|
2018-07-05 12:26:54 +00:00
|
|
|
* happen since fake-MST encoders don't set their get_power_domains()
|
|
|
|
* hook.
|
2018-06-21 18:44:49 +00:00
|
|
|
*/
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
if (drm_WARN_ON(&dev_priv->drm,
|
|
|
|
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
|
2019-04-07 12:46:55 +00:00
|
|
|
return;
|
2018-07-05 12:26:54 +00:00
|
|
|
|
2019-12-04 18:05:43 +00:00
|
|
|
dig_port = enc_to_dig_port(encoder);
|
2020-03-30 15:22:44 +00:00
|
|
|
|
2021-09-21 00:23:05 +00:00
|
|
|
if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
|
2020-11-30 21:21:55 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
|
|
|
|
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain);
|
|
|
|
}
|
2018-06-21 18:44:49 +00:00
|
|
|
|
2022-11-14 12:22:50 +00:00
|
|
|
main_link_aux_power_domain_get(dig_port, crtc_state);
|
2017-02-24 14:19:59 +00:00
|
|
|
}
|
|
|
|
|
2023-02-13 22:52:47 +00:00
|
|
|
void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2012-10-05 15:05:54 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2017-03-02 12:58:55 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2017-03-02 12:58:56 +00:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2021-05-14 15:36:53 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
|
|
|
u32 val;
|
2012-10-05 15:05:54 +00:00
|
|
|
|
2023-02-13 22:52:48 +00:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP)
|
|
|
|
return;
|
2021-05-14 15:36:53 +00:00
|
|
|
|
2023-02-13 22:52:48 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 13)
|
|
|
|
val = TGL_TRANS_CLK_SEL_PORT(phy);
|
|
|
|
else if (DISPLAY_VER(dev_priv) >= 12)
|
|
|
|
val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
|
|
|
|
else
|
|
|
|
val = TRANS_CLK_SEL_PORT(encoder->port);
|
|
|
|
|
|
|
|
intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
|
2012-10-05 15:05:54 +00:00
|
|
|
}
|
|
|
|
|
2023-02-13 22:52:47 +00:00
|
|
|
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
|
2012-10-05 15:05:54 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
2017-03-02 12:58:56 +00:00
|
|
|
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
|
2023-02-13 22:52:48 +00:00
|
|
|
u32 val;
|
2012-10-05 15:05:54 +00:00
|
|
|
|
2023-02-13 22:52:48 +00:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
|
|
|
val = TGL_TRANS_CLK_SEL_DISABLED;
|
|
|
|
else
|
|
|
|
val = TRANS_CLK_SEL_DISABLED;
|
|
|
|
|
|
|
|
intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
|
2012-10-05 15:05:54 +00:00
|
|
|
}
|
|
|
|
|
2016-07-12 12:59:28 +00:00
|
|
|
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
|
2019-01-18 12:01:21 +00:00
|
|
|
enum port port, u8 iboost)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2016-07-12 12:59:28 +00:00
|
|
|
u32 tmp;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
|
2016-07-12 12:59:28 +00:00
|
|
|
tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
|
|
|
|
if (iboost)
|
|
|
|
tmp |= iboost << BALANCE_LEG_SHIFT(port);
|
|
|
|
else
|
|
|
|
tmp |= BALANCE_LEG_DISABLE(port);
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
|
2016-07-12 12:59:28 +00:00
|
|
|
}
|
|
|
|
|
2017-10-16 14:56:58 +00:00
|
|
|
static void skl_ddi_set_iboost(struct intel_encoder *encoder,
|
2020-10-01 11:10:53 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
int level)
|
2016-07-12 12:59:28 +00:00
|
|
|
{
|
2020-07-01 04:50:54 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2017-11-09 15:24:34 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-01-18 12:01:21 +00:00
|
|
|
u8 iboost;
|
2015-06-25 08:11:03 +00:00
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
2023-02-16 00:04:25 +00:00
|
|
|
iboost = intel_bios_hdmi_boost_level(encoder->devdata);
|
2017-10-16 14:56:58 +00:00
|
|
|
else
|
2023-02-16 00:04:25 +00:00
|
|
|
iboost = intel_bios_dp_boost_level(encoder->devdata);
|
2015-07-10 11:10:55 +00:00
|
|
|
|
2017-10-16 14:56:58 +00:00
|
|
|
if (iboost == 0) {
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2017-10-16 14:56:58 +00:00
|
|
|
int n_entries;
|
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2017-10-18 18:19:34 +00:00
|
|
|
return;
|
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
iboost = trans->entries[level].hsw.i_boost;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure that the requested I_boost is valid */
|
|
|
|
if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
|
2015-06-25 08:11:03 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-07-08 20:55:09 +00:00
|
|
|
_skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
|
2015-06-25 08:11:03 +00:00
|
|
|
|
2020-07-08 20:55:09 +00:00
|
|
|
if (encoder->port == PORT_A && dig_port->max_lanes == 4)
|
2016-07-12 12:59:28 +00:00
|
|
|
_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2017-02-23 17:49:01 +00:00
|
|
|
{
|
2020-05-12 17:41:42 +00:00
|
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
2017-02-23 17:49:01 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
int n_entries;
|
|
|
|
|
2021-06-08 07:35:55 +00:00
|
|
|
encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
2017-02-23 17:49:01 +00:00
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
|
2017-02-23 17:49:01 +00:00
|
|
|
n_entries = 1;
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
if (drm_WARN_ON(&dev_priv->drm,
|
|
|
|
n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
|
2017-02-23 17:49:01 +00:00
|
|
|
n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
|
|
|
|
|
|
|
|
return index_to_dp_signal_levels[n_entries - 1] &
|
|
|
|
DP_TRAIN_VOLTAGE_SWING_MASK;
|
|
|
|
}
|
|
|
|
|
2018-05-17 17:03:06 +00:00
|
|
|
/*
|
|
|
|
* We assume that the full set of pre-emphasis values can be
|
|
|
|
* used on all DDI platforms. Should that change we need to
|
|
|
|
* rethink this code.
|
|
|
|
*/
|
2020-05-12 17:41:42 +00:00
|
|
|
static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
|
2018-05-17 17:03:06 +00:00
|
|
|
{
|
2020-05-12 17:41:42 +00:00
|
|
|
return DP_TRAIN_PRE_EMPH_LEVEL_3;
|
2018-05-17 17:03:06 +00:00
|
|
|
}
|
|
|
|
|
2021-10-06 20:49:27 +00:00
|
|
|
static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
|
|
|
|
int lane)
|
|
|
|
{
|
|
|
|
if (crtc_state->port_clock > 600000)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (crtc_state->lane_count == 4)
|
|
|
|
return lane >= 1 ? LOADGEN_SELECT : 0;
|
|
|
|
else
|
|
|
|
return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
|
|
|
|
}
|
|
|
|
|
2020-07-08 20:55:08 +00:00
|
|
|
static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
|
2021-10-01 13:01:01 +00:00
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-03-28 21:58:02 +00:00
|
|
|
{
|
2020-07-08 20:55:08 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2020-07-08 20:55:09 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
2020-10-01 11:10:53 +00:00
|
|
|
int n_entries, ln;
|
|
|
|
u32 val;
|
2018-03-28 21:58:02 +00:00
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2020-12-07 20:35:12 +00:00
|
|
|
return;
|
2018-03-28 21:58:02 +00:00
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
|
2020-07-15 17:56:37 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
|
|
|
|
val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
|
2021-09-27 18:24:47 +00:00
|
|
|
intel_dp->hobl_active = is_hobl_buf_trans(trans);
|
2020-07-15 17:56:37 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
|
|
|
|
intel_dp->hobl_active ? val : 0);
|
|
|
|
}
|
|
|
|
|
2018-12-17 22:13:47 +00:00
|
|
|
/* Set PORT_TX_DW5 */
|
2021-10-06 20:49:25 +00:00
|
|
|
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
|
2018-12-17 22:13:47 +00:00
|
|
|
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
|
|
|
|
TAP2_DISABLE | TAP3_DISABLE);
|
|
|
|
val |= SCALING_MODE_SEL(0x2);
|
2018-03-28 21:58:02 +00:00
|
|
|
val |= RTERM_SELECT(0x6);
|
2018-12-17 22:13:47 +00:00
|
|
|
val |= TAP3_DISABLE;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* Program PORT_TX_DW2 */
|
2021-10-06 20:49:28 +00:00
|
|
|
for (ln = 0; ln < 4; ln++) {
|
2021-10-06 20:49:29 +00:00
|
|
|
int level = intel_ddi_level(encoder, crtc_state, ln);
|
|
|
|
|
2021-10-06 20:49:36 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
|
|
|
|
SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
|
|
|
|
SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
|
|
|
|
SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
|
|
|
|
RCOMP_SCALAR(0x98));
|
2021-10-06 20:49:28 +00:00
|
|
|
}
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* Program PORT_TX_DW4 */
|
|
|
|
/* We cannot write to GRP. It would overwrite individual loadgen. */
|
2021-10-06 20:49:24 +00:00
|
|
|
for (ln = 0; ln < 4; ln++) {
|
2021-10-06 20:49:29 +00:00
|
|
|
int level = intel_ddi_level(encoder, crtc_state, ln);
|
|
|
|
|
2021-10-06 20:49:36 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
|
|
|
|
POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
|
|
|
|
POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
|
|
|
|
POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
|
|
|
|
CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
|
2018-03-28 21:58:02 +00:00
|
|
|
}
|
2018-12-17 22:13:47 +00:00
|
|
|
|
|
|
|
/* Program PORT_TX_DW7 */
|
2021-10-06 20:49:28 +00:00
|
|
|
for (ln = 0; ln < 4; ln++) {
|
2021-10-06 20:49:29 +00:00
|
|
|
int level = intel_ddi_level(encoder, crtc_state, ln);
|
|
|
|
|
2021-10-06 20:49:36 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
|
|
|
|
N_SCALAR_MASK,
|
|
|
|
N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
|
2021-10-06 20:49:28 +00:00
|
|
|
}
|
2018-03-28 21:58:02 +00:00
|
|
|
}
|
|
|
|
|
2021-10-01 13:01:01 +00:00
|
|
|
static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-03-28 21:58:02 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-07-09 18:39:32 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
2018-03-28 21:58:02 +00:00
|
|
|
u32 val;
|
2021-10-06 20:49:27 +00:00
|
|
|
int ln;
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* 1. If port type is eDP or DP,
|
|
|
|
* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
|
|
|
|
* else clear to 0b.
|
|
|
|
*/
|
2021-10-06 20:49:25 +00:00
|
|
|
val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
|
2020-10-01 11:10:53 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
2018-03-28 21:58:02 +00:00
|
|
|
val &= ~COMMON_KEEPER_EN;
|
|
|
|
else
|
|
|
|
val |= COMMON_KEEPER_EN;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* 2. Program loadgen select */
|
|
|
|
/*
|
2021-10-06 20:49:25 +00:00
|
|
|
* Program PORT_TX_DW4 depending on Bit rate and used lanes
|
2018-03-28 21:58:02 +00:00
|
|
|
* <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
|
|
|
|
* <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
|
|
|
|
* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
|
|
|
|
*/
|
2021-10-06 20:49:24 +00:00
|
|
|
for (ln = 0; ln < 4; ln++) {
|
2021-10-06 20:49:36 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
|
|
|
|
LOADGEN_SELECT,
|
|
|
|
icl_combo_phy_loadgen_select(crtc_state, ln));
|
2018-03-28 21:58:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
|
2021-10-06 20:49:36 +00:00
|
|
|
intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
|
|
|
|
0, SUS_CLOCK_CONFIG);
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* 4. Clear training enable to change swing values */
|
2021-10-06 20:49:25 +00:00
|
|
|
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
|
2018-03-28 21:58:02 +00:00
|
|
|
val &= ~TX_TRAINING_EN;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* 5. Program swing and de-emphasis */
|
2021-10-01 13:01:01 +00:00
|
|
|
icl_ddi_combo_vswing_program(encoder, crtc_state);
|
2018-03-28 21:58:02 +00:00
|
|
|
|
|
|
|
/* 6. Set training enable to trigger update */
|
2021-10-06 20:49:25 +00:00
|
|
|
val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
|
2018-03-28 21:58:02 +00:00
|
|
|
val |= TX_TRAINING_EN;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
|
2018-03-28 21:58:02 +00:00
|
|
|
}
|
|
|
|
|
2021-10-01 13:01:01 +00:00
|
|
|
static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-06-28 22:35:44 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-10-01 19:37:29 +00:00
|
|
|
enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2020-10-01 11:10:53 +00:00
|
|
|
int n_entries, ln;
|
2018-06-28 22:35:44 +00:00
|
|
|
|
2021-09-21 00:23:05 +00:00
|
|
|
if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
|
2021-01-28 15:59:44 +00:00
|
|
|
return;
|
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2020-12-07 20:35:12 +00:00
|
|
|
return;
|
2018-06-28 22:35:44 +00:00
|
|
|
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
|
|
|
|
CRI_USE_FS32, 0);
|
|
|
|
intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
|
|
|
|
CRI_USE_FS32, 0);
|
2018-06-28 22:35:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Program MG_TX_SWINGCTRL with values from vswing table */
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:30 +00:00
|
|
|
int level;
|
|
|
|
|
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
|
|
|
|
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
|
2018-06-28 22:35:44 +00:00
|
|
|
|
2021-10-06 20:49:30 +00:00
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
|
|
|
|
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
|
2018-06-28 22:35:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Program MG_TX_DRVCTRL with values from vswing table */
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:30 +00:00
|
|
|
int level;
|
|
|
|
|
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
|
|
|
|
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_EN);
|
2018-06-28 22:35:44 +00:00
|
|
|
|
2021-10-06 20:49:30 +00:00
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
|
|
|
|
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
|
|
|
|
CRI_TXDEEMPH_OVERRIDE_EN);
|
2018-06-28 22:35:44 +00:00
|
|
|
|
|
|
|
/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program MG_CLKHUB<LN, port being used> with value from frequency table
|
|
|
|
* In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
|
|
|
|
* values from table for which TX1 and TX2 enabled.
|
|
|
|
*/
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
|
|
|
|
CFG_LOW_RATE_LKREN_EN,
|
|
|
|
crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
|
2018-06-28 22:35:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_EN,
|
|
|
|
crtc_state->port_clock > 500000 ?
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
|
|
|
|
|
|
|
|
intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_EN,
|
|
|
|
crtc_state->port_clock > 500000 ?
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
|
|
|
|
CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
|
2018-06-28 22:35:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Program MG_TX_PISO_READLOAD with values from vswing table */
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:35 +00:00
|
|
|
intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
|
|
|
|
0, CRI_CALCINIT);
|
|
|
|
intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
|
|
|
|
0, CRI_CALCINIT);
|
2018-06-28 22:35:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-01 13:01:01 +00:00
|
|
|
static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2019-09-26 21:06:57 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
|
2021-09-27 18:24:47 +00:00
|
|
|
const struct intel_ddi_buf_trans *trans;
|
2020-10-01 11:10:53 +00:00
|
|
|
int n_entries, ln;
|
2019-09-26 21:06:57 +00:00
|
|
|
|
2021-09-21 00:23:05 +00:00
|
|
|
if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
|
2021-01-28 15:59:44 +00:00
|
|
|
return;
|
|
|
|
|
2021-09-27 18:24:47 +00:00
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
|
2020-12-07 20:35:12 +00:00
|
|
|
return;
|
2019-09-26 21:06:57 +00:00
|
|
|
|
|
|
|
for (ln = 0; ln < 2; ln++) {
|
2021-10-06 20:49:31 +00:00
|
|
|
int level;
|
|
|
|
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
|
2019-10-21 22:34:08 +00:00
|
|
|
|
2021-10-06 20:49:31 +00:00
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
|
|
|
|
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
|
2022-10-25 11:44:55 +00:00
|
|
|
DKL_TX_PRESHOOT_COEFF_MASK |
|
|
|
|
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
|
|
|
|
DKL_TX_VSWING_CONTROL_MASK,
|
|
|
|
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
|
|
|
|
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
|
|
|
|
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
|
2019-09-26 21:06:57 +00:00
|
|
|
|
2021-10-06 20:49:31 +00:00
|
|
|
level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
|
|
|
|
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
|
2022-10-25 11:44:55 +00:00
|
|
|
DKL_TX_PRESHOOT_COEFF_MASK |
|
|
|
|
DKL_TX_DE_EMPAHSIS_COEFF_MASK |
|
|
|
|
DKL_TX_VSWING_CONTROL_MASK,
|
|
|
|
DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
|
|
|
|
DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
|
|
|
|
DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
|
2021-10-06 20:49:34 +00:00
|
|
|
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
|
2022-10-25 11:44:55 +00:00
|
|
|
DKL_TX_DP20BITMODE, 0);
|
2022-01-13 17:48:26 +00:00
|
|
|
|
|
|
|
if (IS_ALDERLAKE_P(dev_priv)) {
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
|
|
|
if (ln == 0) {
|
|
|
|
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
|
|
|
|
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
|
|
|
|
} else {
|
|
|
|
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
|
|
|
|
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
|
|
|
|
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
|
|
|
|
}
|
|
|
|
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
|
2022-10-25 11:44:55 +00:00
|
|
|
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
|
|
|
|
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
|
|
|
|
val);
|
2022-01-13 17:48:26 +00:00
|
|
|
}
|
2019-09-26 21:06:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static int translate_signal_level(struct intel_dp *intel_dp,
|
|
|
|
u8 signal_levels)
|
2015-06-25 08:11:03 +00:00
|
|
|
{
|
2020-04-06 11:27:45 +00:00
|
|
|
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
2017-02-23 17:35:06 +00:00
|
|
|
int i;
|
2015-06-25 08:11:03 +00:00
|
|
|
|
2017-02-23 17:35:06 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
|
|
|
|
if (index_to_dp_signal_levels[i] == signal_levels)
|
|
|
|
return i;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
2020-04-06 11:27:45 +00:00
|
|
|
drm_WARN(&i915->drm, 1,
|
|
|
|
"Unsupported voltage swing/pre-emphasis level: 0x%x\n",
|
|
|
|
signal_levels);
|
2017-02-23 17:35:06 +00:00
|
|
|
|
|
|
|
return 0;
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
2021-10-11 18:21:44 +00:00
|
|
|
static int intel_ddi_dp_level(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
int lane)
|
2017-08-29 23:22:23 +00:00
|
|
|
{
|
2021-10-01 13:01:05 +00:00
|
|
|
u8 train_set = intel_dp->train_set[lane];
|
2017-08-29 23:22:23 +00:00
|
|
|
|
2021-10-11 18:21:44 +00:00
|
|
|
if (intel_dp_is_uhbr(crtc_state)) {
|
|
|
|
return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
|
|
|
|
} else {
|
|
|
|
u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
|
|
|
|
return translate_signal_level(intel_dp, signal_levels);
|
|
|
|
}
|
2017-08-29 23:22:23 +00:00
|
|
|
}
|
|
|
|
|
2021-10-01 13:01:01 +00:00
|
|
|
int intel_ddi_level(struct intel_encoder *encoder,
|
2021-10-01 13:01:05 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
int lane)
|
2021-10-01 13:01:00 +00:00
|
|
|
{
|
2021-10-01 13:01:03 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_ddi_buf_trans *trans;
|
|
|
|
int level, n_entries;
|
|
|
|
|
|
|
|
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
|
|
|
|
if (drm_WARN_ON_ONCE(&i915->drm, !trans))
|
|
|
|
return 0;
|
|
|
|
|
2021-10-01 13:01:00 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
2021-10-01 13:01:04 +00:00
|
|
|
level = intel_ddi_hdmi_level(encoder, trans);
|
2021-10-01 13:01:00 +00:00
|
|
|
else
|
2021-10-11 18:21:44 +00:00
|
|
|
level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
|
|
|
|
lane);
|
2021-10-01 13:01:03 +00:00
|
|
|
|
|
|
|
if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
|
|
|
|
level = n_entries - 1;
|
|
|
|
|
|
|
|
return level;
|
2021-10-01 13:01:00 +00:00
|
|
|
}
|
|
|
|
|
2020-04-20 20:06:08 +00:00
|
|
|
static void
|
2021-10-01 13:01:00 +00:00
|
|
|
hsw_set_signal_levels(struct intel_encoder *encoder,
|
2020-10-01 11:10:53 +00:00
|
|
|
const struct intel_crtc_state *crtc_state)
|
2020-04-20 20:06:08 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2021-10-01 13:01:00 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2021-10-01 13:01:05 +00:00
|
|
|
int level = intel_ddi_level(encoder, crtc_state, 0);
|
2020-04-20 20:06:08 +00:00
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 signal_levels;
|
|
|
|
|
2021-10-01 13:01:00 +00:00
|
|
|
if (has_iboost(dev_priv))
|
|
|
|
skl_ddi_set_iboost(encoder, crtc_state, level);
|
|
|
|
|
|
|
|
/* HDMI ignores the rest */
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
|
|
|
return;
|
|
|
|
|
2020-04-20 20:06:08 +00:00
|
|
|
signal_levels = DDI_BUF_TRANS_SELECT(level);
|
|
|
|
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
|
|
|
signal_levels);
|
|
|
|
|
|
|
|
intel_dp->DP &= ~DDI_BUF_EMP_MASK;
|
|
|
|
intel_dp->DP |= signal_levels;
|
|
|
|
|
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
|
|
|
|
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
|
2015-06-25 08:11:03 +00:00
|
|
|
}
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
2021-02-05 21:46:30 +00:00
|
|
|
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
|
|
|
|
{
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
2021-02-05 21:46:30 +00:00
|
|
|
|
|
|
|
intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* "This step and the step before must be
|
|
|
|
* done with separate register writes."
|
|
|
|
*/
|
|
|
|
intel_de_rmw(i915, reg, clk_off, 0);
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
2021-02-05 21:46:30 +00:00
|
|
|
}
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
|
2021-02-05 21:46:30 +00:00
|
|
|
u32 clk_off)
|
|
|
|
{
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
2021-02-05 21:46:30 +00:00
|
|
|
|
|
|
|
intel_de_rmw(i915, reg, 0, clk_off);
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
2021-02-05 21:46:30 +00:00
|
|
|
}
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
|
2021-02-24 14:42:13 +00:00
|
|
|
u32 clk_off)
|
|
|
|
{
|
|
|
|
return !(intel_de_read(i915, reg) & clk_off);
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
|
2021-02-24 14:42:12 +00:00
|
|
|
u32 clk_sel_mask, u32 clk_sel_shift)
|
|
|
|
{
|
|
|
|
enum intel_dpll_id id;
|
|
|
|
|
|
|
|
id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:31 +00:00
|
|
|
static void adls_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
2021-02-05 21:46:31 +00:00
|
|
|
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
|
|
|
|
pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
|
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void adls_ddi_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
|
2021-02-05 21:46:31 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
|
2021-02-24 14:42:13 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
|
2021-02-24 14:42:12 +00:00
|
|
|
ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
|
|
|
|
ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:31 +00:00
|
|
|
static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-05 21:46:31 +00:00
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-05 21:46:31 +00:00
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-24 14:42:13 +00:00
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-24 14:42:12 +00:00
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
|
|
|
RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:25 +00:00
|
|
|
static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2020-11-06 21:00:06 +00:00
|
|
|
{
|
2021-02-05 21:46:34 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2021-02-05 21:46:30 +00:00
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
2021-02-05 21:46:34 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2020-11-06 21:00:06 +00:00
|
|
|
|
2021-02-05 21:46:34 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
2021-02-05 21:46:29 +00:00
|
|
|
return;
|
|
|
|
|
2020-11-06 21:00:06 +00:00
|
|
|
/*
|
|
|
|
* If we fail this, something went very wrong: first 2 PLLs should be
|
|
|
|
* used by first 2 phys and last 2 PLLs by last phys
|
|
|
|
*/
|
2021-02-05 21:46:34 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm,
|
2020-11-06 21:00:06 +00:00
|
|
|
(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
|
|
|
|
(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
|
|
|
|
return;
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
2021-02-05 21:46:30 +00:00
|
|
|
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
|
|
|
DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
|
|
|
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
2020-11-06 21:00:06 +00:00
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:25 +00:00
|
|
|
static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
2021-02-05 21:46:34 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2021-02-05 21:46:25 +00:00
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
|
2021-02-05 21:46:30 +00:00
|
|
|
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
2021-02-05 21:46:25 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
|
2021-02-24 14:42:13 +00:00
|
|
|
DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2021-06-30 21:05:22 +00:00
|
|
|
enum intel_dpll_id id;
|
|
|
|
u32 val;
|
2021-02-24 14:42:12 +00:00
|
|
|
|
2021-06-30 21:05:22 +00:00
|
|
|
val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
|
|
|
|
val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
|
|
|
|
val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
|
|
|
|
id = val;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
|
|
|
|
* and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
|
|
|
|
* bit for phy C and D.
|
|
|
|
*/
|
|
|
|
if (phy >= PHY_C)
|
|
|
|
id += DPLL_ID_DG1_DPLL2;
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
2021-02-24 14:42:12 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-04-27 23:14:36 +00:00
|
|
|
{
|
2021-02-05 21:46:34 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2021-02-05 21:46:30 +00:00
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
2021-02-05 21:46:34 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2018-04-27 23:14:36 +00:00
|
|
|
|
2021-02-05 21:46:34 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
2021-02-05 21:46:29 +00:00
|
|
|
return;
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-05 21:46:31 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
|
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
2018-04-27 23:14:36 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
|
2018-04-27 23:14:36 +00:00
|
|
|
{
|
2021-02-05 21:46:34 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2021-01-25 14:07:49 +00:00
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
_icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-05 21:46:31 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
2018-04-27 23:14:36 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-24 14:42:13 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2021-07-28 21:59:27 +00:00
|
|
|
return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
|
2021-02-24 14:42:12 +00:00
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
|
|
|
|
ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
|
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2012-10-05 15:05:58 +00:00
|
|
|
{
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
|
|
|
|
* MG does not exist, but the programming is required to ungate DDIC and DDID."
|
|
|
|
*/
|
|
|
|
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
|
|
|
|
|
|
|
|
icl_ddi_combo_enable_clock(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
icl_ddi_combo_disable_clock(encoder);
|
|
|
|
|
|
|
|
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, DDI_CLK_SEL(port));
|
|
|
|
|
|
|
|
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return icl_ddi_combo_is_clock_enabled(encoder);
|
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2018-10-04 09:46:00 +00:00
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
|
|
|
enum port port = encoder->port;
|
2012-10-05 15:05:58 +00:00
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
2016-09-01 22:08:07 +00:00
|
|
|
return;
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
intel_de_write(i915, DDI_CLK_SEL(port),
|
|
|
|
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
|
2017-12-15 22:43:10 +00:00
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
2017-12-15 22:43:10 +00:00
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
|
|
|
|
ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
2015-08-17 15:46:20 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
|
2017-10-10 12:12:00 +00:00
|
|
|
{
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2017-10-10 12:12:00 +00:00
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
|
|
|
|
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
|
|
|
|
0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
|
|
|
|
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
|
2017-10-10 12:12:00 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, DDI_CLK_SEL(port));
|
|
|
|
|
|
|
|
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
|
|
|
|
|
|
|
|
return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
enum intel_dpll_id id;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, DDI_CLK_SEL(port));
|
|
|
|
|
|
|
|
switch (tmp & DDI_CLK_SEL_MASK) {
|
|
|
|
case DDI_CLK_SEL_TBT_162:
|
|
|
|
case DDI_CLK_SEL_TBT_270:
|
|
|
|
case DDI_CLK_SEL_TBT_540:
|
|
|
|
case DDI_CLK_SEL_TBT_810:
|
|
|
|
id = DPLL_ID_ICL_TBTPLL;
|
|
|
|
break;
|
|
|
|
case DDI_CLK_SEL_MG:
|
|
|
|
id = icl_tc_port_to_pll_id(tc_port);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(tmp);
|
|
|
|
fallthrough;
|
|
|
|
case DDI_CLK_SEL_NONE:
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum intel_dpll_id id;
|
|
|
|
|
|
|
|
switch (encoder->port) {
|
|
|
|
case PORT_A:
|
|
|
|
id = DPLL_ID_SKL_DPLL0;
|
|
|
|
break;
|
|
|
|
case PORT_B:
|
|
|
|
id = DPLL_ID_SKL_DPLL1;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
id = DPLL_ID_SKL_DPLL2;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(encoder->port);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:23 +00:00
|
|
|
static void skl_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
2021-02-05 21:46:23 +00:00
|
|
|
|
2021-02-05 21:46:27 +00:00
|
|
|
intel_de_rmw(i915, DPLL_CTRL2,
|
|
|
|
DPLL_CTRL2_DDI_CLK_OFF(port) |
|
|
|
|
DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
|
|
|
|
DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
|
|
|
|
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
|
2021-02-05 21:46:23 +00:00
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
2021-02-05 21:46:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_ddi_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_lock(&i915->display.dpll.lock);
|
2021-02-05 21:46:28 +00:00
|
|
|
|
2021-02-05 21:46:27 +00:00
|
|
|
intel_de_rmw(i915, DPLL_CTRL2,
|
|
|
|
0, DPLL_CTRL2_DDI_CLK_OFF(port));
|
2021-02-05 21:46:28 +00:00
|
|
|
|
2022-08-24 13:15:38 +00:00
|
|
|
mutex_unlock(&i915->display.dpll.lock);
|
2021-02-05 21:46:23 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME Not sure if the override affects both
|
|
|
|
* the PLL selection and the CLK_OFF bit.
|
|
|
|
*/
|
|
|
|
return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
enum intel_dpll_id id;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, DPLL_CTRL2);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME Not sure if the override affects both
|
|
|
|
* the PLL selection and the CLK_OFF bit.
|
|
|
|
*/
|
|
|
|
if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
|
|
|
|
DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:22 +00:00
|
|
|
void hsw_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
|
|
|
|
}
|
|
|
|
|
|
|
|
void hsw_ddi_disable_clock(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:13 +00:00
|
|
|
bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
enum intel_dpll_id id;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
tmp = intel_de_read(i915, PORT_CLK_SEL(port));
|
|
|
|
|
|
|
|
switch (tmp & PORT_CLK_SEL_MASK) {
|
|
|
|
case PORT_CLK_SEL_WRPLL1:
|
|
|
|
id = DPLL_ID_WRPLL1;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_WRPLL2:
|
|
|
|
id = DPLL_ID_WRPLL2;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_SPLL:
|
|
|
|
id = DPLL_ID_SPLL;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_810:
|
|
|
|
id = DPLL_ID_LCPLL_810;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_1350:
|
|
|
|
id = DPLL_ID_LCPLL_1350;
|
|
|
|
break;
|
|
|
|
case PORT_CLK_SEL_LCPLL_2700:
|
|
|
|
id = DPLL_ID_LCPLL_2700;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(tmp);
|
|
|
|
fallthrough;
|
|
|
|
case PORT_CLK_SEL_NONE:
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return intel_get_shared_dpll_by_id(i915, id);
|
|
|
|
}
|
|
|
|
|
2021-02-05 21:46:21 +00:00
|
|
|
void intel_ddi_enable_clock(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
if (encoder->enable_clock)
|
|
|
|
encoder->enable_clock(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2021-10-15 07:16:24 +00:00
|
|
|
void intel_ddi_disable_clock(struct intel_encoder *encoder)
|
2021-02-05 21:46:21 +00:00
|
|
|
{
|
|
|
|
if (encoder->disable_clock)
|
|
|
|
encoder->disable_clock(encoder);
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:14 +00:00
|
|
|
void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
|
2021-02-05 21:46:33 +00:00
|
|
|
{
|
2021-02-05 21:46:34 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2021-02-05 21:46:33 +00:00
|
|
|
u32 port_mask;
|
|
|
|
bool ddi_clk_needed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In case of DP MST, we sanitize the primary encoder only, not the
|
|
|
|
* virtual ones.
|
|
|
|
*/
|
|
|
|
if (encoder->type == INTEL_OUTPUT_DP_MST)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
|
|
|
|
u8 pipe_mask;
|
|
|
|
bool is_mst;
|
|
|
|
|
|
|
|
intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
|
|
|
|
/*
|
|
|
|
* In the unlikely case that BIOS enables DP in MST mode, just
|
|
|
|
* warn since our MST HW readout is incomplete.
|
|
|
|
*/
|
2021-02-05 21:46:34 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, is_mst))
|
2021-02-05 21:46:33 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
port_mask = BIT(encoder->port);
|
|
|
|
ddi_clk_needed = encoder->base.crtc;
|
|
|
|
|
|
|
|
if (encoder->type == INTEL_OUTPUT_DSI) {
|
|
|
|
struct intel_encoder *other_encoder;
|
|
|
|
|
|
|
|
port_mask = intel_dsi_encoder_ports(encoder);
|
|
|
|
/*
|
|
|
|
* Sanity check that we haven't incorrectly registered another
|
|
|
|
* encoder using any of the ports of this DSI encoder.
|
|
|
|
*/
|
2021-02-05 21:46:34 +00:00
|
|
|
for_each_intel_encoder(&i915->drm, other_encoder) {
|
2021-02-05 21:46:33 +00:00
|
|
|
if (other_encoder == encoder)
|
|
|
|
continue;
|
|
|
|
|
2021-02-05 21:46:34 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm,
|
2021-02-05 21:46:33 +00:00
|
|
|
port_mask & BIT(other_encoder->port)))
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* For DSI we keep the ddi clocks gated
|
|
|
|
* except during enable/disable sequence.
|
|
|
|
*/
|
|
|
|
ddi_clk_needed = false;
|
|
|
|
}
|
|
|
|
|
2021-07-23 17:42:35 +00:00
|
|
|
if (ddi_clk_needed || !encoder->is_clock_enabled ||
|
2021-02-24 14:42:13 +00:00
|
|
|
!encoder->is_clock_enabled(encoder))
|
|
|
|
return;
|
|
|
|
|
|
|
|
drm_notice(&i915->drm,
|
|
|
|
"[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
|
|
|
|
encoder->base.base.id, encoder->base.name);
|
|
|
|
|
|
|
|
encoder->disable_clock(encoder);
|
2021-02-05 21:46:33 +00:00
|
|
|
}
|
|
|
|
|
2019-09-26 21:06:56 +00:00
|
|
|
static void
|
2020-07-01 04:50:54 +00:00
|
|
|
icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
|
2019-09-26 21:06:56 +00:00
|
|
|
const struct intel_crtc_state *crtc_state)
|
2018-11-02 19:26:56 +00:00
|
|
|
{
|
2020-07-01 04:50:54 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
|
2021-01-28 15:59:48 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
|
2019-09-26 21:06:56 +00:00
|
|
|
u32 ln0, ln1, pin_assignment;
|
|
|
|
u8 width;
|
2018-11-02 19:26:56 +00:00
|
|
|
|
2021-01-28 15:59:48 +00:00
|
|
|
if (!intel_phy_is_tc(dev_priv, phy) ||
|
2021-09-21 00:23:05 +00:00
|
|
|
intel_tc_port_in_tbt_alt_mode(dig_port))
|
2018-11-02 19:26:56 +00:00
|
|
|
return;
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2022-10-25 11:44:57 +00:00
|
|
|
ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
|
|
|
|
ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
|
2019-09-26 21:06:57 +00:00
|
|
|
} else {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
|
|
|
|
ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
|
2019-09-26 21:06:57 +00:00
|
|
|
}
|
2018-11-02 19:26:56 +00:00
|
|
|
|
2020-06-08 20:45:37 +00:00
|
|
|
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
|
2019-09-26 21:06:56 +00:00
|
|
|
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
|
2018-11-02 19:26:56 +00:00
|
|
|
|
2019-09-26 21:06:56 +00:00
|
|
|
/* DPPATC */
|
2020-07-01 04:50:54 +00:00
|
|
|
pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
|
2019-09-26 21:06:56 +00:00
|
|
|
width = crtc_state->lane_count;
|
2018-11-02 19:26:56 +00:00
|
|
|
|
2019-09-26 21:06:56 +00:00
|
|
|
switch (pin_assignment) {
|
|
|
|
case 0x0:
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm,
|
2021-09-21 00:23:05 +00:00
|
|
|
!intel_tc_port_in_legacy_mode(dig_port));
|
2019-09-26 21:06:56 +00:00
|
|
|
if (width == 1) {
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
|
|
|
|
} else {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x1:
|
|
|
|
if (width == 4) {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x2:
|
|
|
|
if (width == 2) {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x3:
|
|
|
|
case 0x5:
|
|
|
|
if (width == 1) {
|
2018-11-02 19:26:56 +00:00
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
|
2019-09-26 21:06:56 +00:00
|
|
|
} else {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
2018-11-02 19:26:56 +00:00
|
|
|
}
|
|
|
|
break;
|
2019-09-26 21:06:56 +00:00
|
|
|
case 0x4:
|
|
|
|
case 0x6:
|
|
|
|
if (width == 1) {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
|
|
|
|
} else {
|
|
|
|
ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
|
|
|
|
}
|
2018-11-02 19:26:56 +00:00
|
|
|
break;
|
|
|
|
default:
|
2019-09-26 21:06:56 +00:00
|
|
|
MISSING_CASE(pin_assignment);
|
2018-11-02 19:26:56 +00:00
|
|
|
}
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
|
|
|
|
intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
|
2019-09-26 21:06:57 +00:00
|
|
|
} else {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
|
|
|
|
intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
|
2019-09-26 21:06:57 +00:00
|
|
|
}
|
2018-11-02 19:26:56 +00:00
|
|
|
}
|
|
|
|
|
2020-09-29 23:34:49 +00:00
|
|
|
static enum transcoder
|
|
|
|
tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
|
|
|
|
return crtc_state->mst_master_transcoder;
|
|
|
|
else
|
|
|
|
return crtc_state->cpu_transcoder;
|
|
|
|
}
|
|
|
|
|
|
|
|
i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2020-09-29 23:34:49 +00:00
|
|
|
return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
|
|
|
|
else
|
|
|
|
return DP_TP_CTL(encoder->port);
|
|
|
|
}
|
|
|
|
|
|
|
|
i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2020-09-29 23:34:49 +00:00
|
|
|
return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
|
|
|
|
else
|
|
|
|
return DP_TP_STATUS(encoder->port);
|
|
|
|
}
|
|
|
|
|
2021-01-22 23:26:42 +00:00
|
|
|
static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
|
|
|
|
|
|
|
if (!crtc_state->vrr.enable)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
|
|
|
|
enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
|
|
|
|
drm_dbg_kms(&i915->drm,
|
2021-04-16 17:10:10 +00:00
|
|
|
"Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
|
2022-02-25 23:46:29 +00:00
|
|
|
str_enable_disable(enable));
|
2021-01-22 23:26:42 +00:00
|
|
|
}
|
|
|
|
|
2018-11-28 20:26:26 +00:00
|
|
|
static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
|
|
|
|
|
2018-11-28 20:26:26 +00:00
|
|
|
if (!crtc_state->fec_enable)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&i915->drm,
|
|
|
|
"Failed to set FEC_READY in the sink\n");
|
2018-11-28 20:26:26 +00:00
|
|
|
}
|
|
|
|
|
2018-11-28 20:26:27 +00:00
|
|
|
static void intel_ddi_enable_fec(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
|
|
|
if (!crtc_state->fec_enable)
|
|
|
|
return;
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
|
|
|
|
0, DP_TP_CTL_FEC_ENABLE);
|
2018-11-28 20:26:27 +00:00
|
|
|
}
|
|
|
|
|
2018-11-28 20:26:28 +00:00
|
|
|
static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
|
|
|
if (!crtc_state->fec_enable)
|
|
|
|
return;
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
|
|
|
|
DP_TP_CTL_FEC_ENABLE, 0);
|
2020-09-29 23:34:49 +00:00
|
|
|
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
2018-11-28 20:26:28 +00:00
|
|
|
}
|
|
|
|
|
2021-01-28 15:59:45 +00:00
|
|
|
static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
|
|
|
if (intel_phy_is_combo(i915, phy)) {
|
|
|
|
bool lane_reversal =
|
|
|
|
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
|
|
|
|
|
|
|
|
intel_combo_phy_power_up_lanes(i915, phy, false,
|
|
|
|
crtc_state->lane_count,
|
|
|
|
lane_reversal);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-08-12 13:23:54 +00:00
|
|
|
/* Splitter enable for eDP MSO is limited to certain pipes. */
|
|
|
|
static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
if (IS_ALDERLAKE_P(i915))
|
|
|
|
return BIT(PIPE_A) | BIT(PIPE_B);
|
|
|
|
else
|
|
|
|
return BIT(PIPE_A);
|
|
|
|
}
|
|
|
|
|
2021-03-02 11:02:59 +00:00
|
|
|
static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
|
|
|
{
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
|
|
|
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
u32 dss1;
|
|
|
|
|
|
|
|
if (!HAS_MSO(i915))
|
|
|
|
return;
|
|
|
|
|
|
|
|
dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
|
|
|
|
|
|
|
|
pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
|
|
|
|
if (!pipe_config->splitter.enable)
|
|
|
|
return;
|
|
|
|
|
2021-08-12 13:23:54 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
|
2021-03-02 11:02:59 +00:00
|
|
|
pipe_config->splitter.enable = false;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
|
|
|
|
default:
|
|
|
|
drm_WARN(&i915->drm, true,
|
|
|
|
"Invalid splitter configuration, dss1=0x%08x\n", dss1);
|
|
|
|
fallthrough;
|
|
|
|
case SPLITTER_CONFIGURATION_2_SEGMENT:
|
|
|
|
pipe_config->splitter.link_count = 2;
|
|
|
|
break;
|
|
|
|
case SPLITTER_CONFIGURATION_4_SEGMENT:
|
|
|
|
pipe_config->splitter.link_count = 4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
|
|
|
|
}
|
|
|
|
|
2021-03-02 11:03:02 +00:00
|
|
|
static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
|
|
|
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
u32 dss1 = 0;
|
|
|
|
|
|
|
|
if (!HAS_MSO(i915))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (crtc_state->splitter.enable) {
|
|
|
|
dss1 |= SPLITTER_ENABLE;
|
|
|
|
dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
|
|
|
|
if (crtc_state->splitter.link_count == 2)
|
|
|
|
dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
|
|
|
|
else
|
|
|
|
dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
|
|
|
|
SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
|
|
|
|
OVERLAP_PIXELS_MASK, dss1);
|
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
static u8 mtl_get_port_width(u8 lane_count)
|
|
|
|
{
|
|
|
|
switch (lane_count) {
|
|
|
|
case 1:
|
|
|
|
return 0;
|
|
|
|
case 2:
|
|
|
|
return 1;
|
|
|
|
case 3:
|
|
|
|
return 4;
|
|
|
|
case 4:
|
|
|
|
return 3;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(lane_count);
|
|
|
|
return 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mtl_ddi_enable_d2d(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
|
|
|
|
XELPDP_PORT_BUF_D2D_LINK_ENABLE);
|
|
|
|
|
|
|
|
if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
|
|
|
|
XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
|
|
|
|
drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
|
|
|
|
val &= ~XELPDP_PORT_WIDTH_MASK;
|
|
|
|
val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
|
|
|
|
|
|
|
|
val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK;
|
|
|
|
if (intel_dp_is_uhbr(crtc_state))
|
|
|
|
val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
|
|
|
|
else
|
|
|
|
val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
|
|
|
|
|
|
|
|
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
|
|
|
|
val |= XELPDP_PORT_REVERSAL;
|
|
|
|
|
|
|
|
intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
|
|
|
|
XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
|
|
|
|
intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
|
|
|
|
XELPDP_PORT_BUF_IO_SELECT_TBT, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
|
|
|
|
|
|
|
|
intel_dp_set_link_params(intel_dp,
|
|
|
|
crtc_state->port_clock,
|
|
|
|
crtc_state->lane_count);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We only configure what the register value will be here. Actual
|
|
|
|
* enabling happens during link training farther down.
|
|
|
|
*/
|
|
|
|
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 1. Enable Power Wells
|
|
|
|
*
|
|
|
|
* This was handled at the beginning of intel_atomic_commit_tail(),
|
|
|
|
* before we called down into this function.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* 2. PMdemand was already set */
|
|
|
|
|
|
|
|
/* 3. Select Thunderbolt */
|
|
|
|
mtl_port_buf_ctl_io_selection(encoder);
|
|
|
|
|
|
|
|
/* 4. Enable Panel Power if PPS is required */
|
|
|
|
intel_pps_on(intel_dp);
|
|
|
|
|
|
|
|
/* 5. Enable the port PLL */
|
|
|
|
intel_ddi_enable_clock(encoder, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 6.a Configure Transcoder Clock Select to direct the Port clock to the
|
|
|
|
* Transcoder.
|
|
|
|
*/
|
|
|
|
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
|
|
|
|
*/
|
|
|
|
intel_ddi_config_transcoder_dp2(encoder, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
|
|
|
|
* Transport Select
|
|
|
|
*/
|
|
|
|
intel_ddi_config_transcoder_func(encoder, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
|
|
|
|
*/
|
|
|
|
intel_ddi_mso_configure(crtc_state);
|
|
|
|
|
|
|
|
if (!is_mst)
|
|
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
|
|
|
|
|
|
|
|
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
|
|
|
|
intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
|
|
|
|
/*
|
|
|
|
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
|
|
|
|
* in the FEC_CONFIGURATION register to 1 before initiating link
|
|
|
|
* training
|
|
|
|
*/
|
|
|
|
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
intel_dp_check_frl_training(intel_dp);
|
|
|
|
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 6. The rest of the below are substeps under the bspec's "Enable and
|
|
|
|
* Train Display Port" step. Note that steps that are specific to
|
|
|
|
* MST will be handled by intel_mst_pre_enable_dp() before/after it
|
|
|
|
* calls into this function. Also intel_mst_pre_enable_dp() only calls
|
|
|
|
* us when active_mst_links==0, so any steps designated for "single
|
|
|
|
* stream or multi-stream master transcoder" can just be performed
|
|
|
|
* unconditionally here.
|
|
|
|
*
|
|
|
|
* mtl_ddi_prepare_link_retrain() that is called by
|
|
|
|
* intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
|
|
|
|
* 6.i and 6.j
|
|
|
|
*
|
|
|
|
* 6.k Follow DisplayPort specification training sequence (see notes for
|
|
|
|
* failure handling)
|
|
|
|
* 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
|
|
|
|
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
|
|
|
|
* (timeout after 800 us)
|
|
|
|
*/
|
|
|
|
intel_dp_start_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
/* 6.n Set DP_TP_CTL link training to Normal */
|
|
|
|
if (!is_trans_port_sync_mode(crtc_state))
|
|
|
|
intel_dp_stop_link_train(intel_dp, crtc_state);
|
|
|
|
|
|
|
|
/* 6.o Configure and enable FEC if needed */
|
|
|
|
intel_ddi_enable_fec(encoder, crtc_state);
|
|
|
|
|
|
|
|
intel_dsc_dp_pps_write(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2019-08-23 08:20:47 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2019-08-23 08:20:47 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2019-08-23 08:20:47 +00:00
|
|
|
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_set_link_params(intel_dp,
|
|
|
|
crtc_state->port_clock,
|
|
|
|
crtc_state->lane_count);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2021-09-30 13:43:08 +00:00
|
|
|
/*
|
|
|
|
* We only configure what the register value will be here. Actual
|
|
|
|
* enabling happens during link training farther down.
|
|
|
|
*/
|
|
|
|
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
|
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 1. Enable Power Wells
|
|
|
|
*
|
|
|
|
* This was handled at the beginning of intel_atomic_commit_tail(),
|
|
|
|
* before we called down into this function.
|
|
|
|
*/
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/* 2. Enable Panel Power if PPS is required */
|
2021-01-08 17:44:12 +00:00
|
|
|
intel_pps_on(intel_dp);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
|
|
|
/*
|
2019-11-07 17:45:27 +00:00
|
|
|
* 3. For non-TBT Type-C ports, set FIA lane count
|
|
|
|
* (DFLEXDPSP.DPX4TXLATC)
|
|
|
|
*
|
|
|
|
* This was done before tgl_ddi_pre_enable_dp by
|
2019-12-24 08:40:05 +00:00
|
|
|
* hsw_crtc_enable()->intel_encoders_pre_pll_enable().
|
2019-08-23 08:20:47 +00:00
|
|
|
*/
|
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 4. Enable the port PLL.
|
|
|
|
*
|
|
|
|
* The PLL enabling itself was already done before this function by
|
2019-12-24 08:40:05 +00:00
|
|
|
* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
|
2019-11-07 17:45:27 +00:00
|
|
|
* configure the PLL to port mapping here.
|
|
|
|
*/
|
2021-02-05 21:46:21 +00:00
|
|
|
intel_ddi_enable_clock(encoder, crtc_state);
|
2019-09-20 20:58:05 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
|
2021-09-21 00:23:05 +00:00
|
|
|
if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
|
2020-11-30 21:21:55 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
|
|
|
|
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain);
|
|
|
|
}
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/* 6. Program DP_MODE */
|
2019-09-26 21:06:56 +00:00
|
|
|
icl_program_mg_dp_mode(dig_port, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
|
|
|
/*
|
2019-11-07 17:45:27 +00:00
|
|
|
* 7. The rest of the below are substeps under the bspec's "Enable and
|
|
|
|
* Train Display Port" step. Note that steps that are specific to
|
|
|
|
* MST will be handled by intel_mst_pre_enable_dp() before/after it
|
|
|
|
* calls into this function. Also intel_mst_pre_enable_dp() only calls
|
|
|
|
* us when active_mst_links==0, so any steps designated for "single
|
|
|
|
* stream or multi-stream master transcoder" can just be performed
|
|
|
|
* unconditionally here.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 7.a Configure Transcoder Clock Select to direct the Port clock to the
|
|
|
|
* Transcoder.
|
2019-08-23 08:20:47 +00:00
|
|
|
*/
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2022-01-19 12:21:50 +00:00
|
|
|
if (HAS_DP20(dev_priv))
|
|
|
|
intel_ddi_config_transcoder_dp2(encoder, crtc_state);
|
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
|
|
|
|
* Transport Select
|
|
|
|
*/
|
2020-04-17 13:47:20 +00:00
|
|
|
intel_ddi_config_transcoder_func(encoder, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 7.c Configure & enable DP_TP_CTL with link training pattern 1
|
|
|
|
* selected
|
|
|
|
*
|
|
|
|
* This will be handled by the intel_dp_start_link_train() farther
|
|
|
|
* down this function.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* 7.e Configure voltage swing and related IO settings */
|
2021-10-01 13:01:00 +00:00
|
|
|
encoder->set_signal_levels(encoder, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
|
|
|
|
* the used lanes of the DDI.
|
|
|
|
*/
|
2021-01-28 15:59:45 +00:00
|
|
|
intel_ddi_power_up_lanes(encoder, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2021-03-02 11:03:02 +00:00
|
|
|
/*
|
|
|
|
* 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
|
|
|
|
*/
|
|
|
|
intel_ddi_mso_configure(crtc_state);
|
|
|
|
|
2019-08-23 08:20:47 +00:00
|
|
|
if (!is_mst)
|
2020-10-16 19:48:00 +00:00
|
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2020-12-18 10:37:23 +00:00
|
|
|
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
|
|
|
|
/*
|
|
|
|
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
|
|
|
|
* in the FEC_CONFIGURATION register to 1 before initiating link
|
|
|
|
* training
|
|
|
|
*/
|
|
|
|
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
|
2019-11-07 17:45:27 +00:00
|
|
|
|
2020-12-18 10:37:18 +00:00
|
|
|
intel_dp_check_frl_training(intel_dp);
|
2020-12-18 10:37:22 +00:00
|
|
|
intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
|
2020-12-18 10:37:18 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/*
|
|
|
|
* 7.i Follow DisplayPort specification training sequence (see notes for
|
|
|
|
* failure handling)
|
|
|
|
* 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
|
|
|
|
* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
|
|
|
|
* (timeout after 800 us)
|
|
|
|
*/
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_start_link_train(intel_dp, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/* 7.k Set DP_TP_CTL link training to Normal */
|
2019-10-18 17:27:23 +00:00
|
|
|
if (!is_trans_port_sync_mode(crtc_state))
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_stop_link_train(intel_dp, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
|
2019-11-07 17:45:27 +00:00
|
|
|
/* 7.l Configure and enable FEC if needed */
|
2019-08-23 08:20:47 +00:00
|
|
|
intel_ddi_enable_fec(encoder, crtc_state);
|
2021-10-22 10:33:01 +00:00
|
|
|
|
|
|
|
intel_dsc_dp_pps_write(encoder, crtc_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2019-08-23 08:20:47 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2015-08-17 15:46:20 +00:00
|
|
|
{
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2016-09-01 22:08:08 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2017-10-10 12:12:06 +00:00
|
|
|
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
|
2016-05-02 19:08:24 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) < 11)
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm,
|
|
|
|
is_mst && (port == PORT_A || port == PORT_E));
|
2020-01-07 17:09:22 +00:00
|
|
|
else
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
|
2017-03-02 12:58:57 +00:00
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_set_link_params(intel_dp,
|
|
|
|
crtc_state->port_clock,
|
|
|
|
crtc_state->lane_count);
|
2017-10-10 12:12:04 +00:00
|
|
|
|
2021-09-30 13:43:08 +00:00
|
|
|
/*
|
|
|
|
* We only configure what the register value will be here. Actual
|
|
|
|
* enabling happens during link training farther down.
|
|
|
|
*/
|
|
|
|
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
|
|
|
|
|
2021-01-08 17:44:12 +00:00
|
|
|
intel_pps_on(intel_dp);
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2021-02-05 21:46:21 +00:00
|
|
|
intel_ddi_enable_clock(encoder, crtc_state);
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2021-09-21 00:23:05 +00:00
|
|
|
if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
|
2020-11-30 21:21:55 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
|
|
|
|
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain);
|
|
|
|
}
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2019-09-26 21:06:56 +00:00
|
|
|
icl_program_mg_dp_mode(dig_port, crtc_state);
|
2018-07-25 00:28:12 +00:00
|
|
|
|
2021-10-01 13:00:59 +00:00
|
|
|
if (has_buf_trans_select(dev_priv))
|
2021-06-08 07:35:47 +00:00
|
|
|
hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
|
2017-08-29 23:22:25 +00:00
|
|
|
|
2021-10-01 13:01:00 +00:00
|
|
|
encoder->set_signal_levels(encoder, crtc_state);
|
|
|
|
|
2021-01-28 15:59:45 +00:00
|
|
|
intel_ddi_power_up_lanes(encoder, crtc_state);
|
2019-04-25 18:52:53 +00:00
|
|
|
|
2018-04-07 01:10:53 +00:00
|
|
|
if (!is_mst)
|
2020-10-16 19:48:00 +00:00
|
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
|
2020-12-18 10:37:23 +00:00
|
|
|
intel_dp_configure_protocol_converter(intel_dp, crtc_state);
|
2018-11-28 20:26:17 +00:00
|
|
|
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
|
|
|
|
true);
|
2018-11-28 20:26:26 +00:00
|
|
|
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_start_link_train(intel_dp, crtc_state);
|
2021-03-20 04:42:42 +00:00
|
|
|
if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
|
2019-10-18 17:27:23 +00:00
|
|
|
!is_trans_port_sync_mode(crtc_state))
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_stop_link_train(intel_dp, crtc_state);
|
2018-06-13 17:27:46 +00:00
|
|
|
|
2018-11-28 20:26:27 +00:00
|
|
|
intel_ddi_enable_fec(encoder, crtc_state);
|
|
|
|
|
2018-08-31 17:47:39 +00:00
|
|
|
if (!is_mst)
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
|
2018-11-28 20:26:19 +00:00
|
|
|
|
2021-10-22 10:33:01 +00:00
|
|
|
intel_dsc_dp_pps_write(encoder, crtc_state);
|
2016-09-01 22:08:08 +00:00
|
|
|
}
|
2015-08-17 15:05:12 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2019-08-23 08:20:47 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
2023-03-02 08:15:32 +00:00
|
|
|
if (HAS_DP20(dev_priv))
|
|
|
|
intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
|
|
|
|
crtc_state);
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
|
|
|
else if (DISPLAY_VER(dev_priv) >= 12)
|
2020-03-13 16:48:30 +00:00
|
|
|
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
else
|
2020-03-13 16:48:30 +00:00
|
|
|
hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
|
2019-09-19 19:53:05 +00:00
|
|
|
|
2019-11-06 21:26:36 +00:00
|
|
|
/* MST will call a setting of MSA after an allocating of Virtual Channel
|
|
|
|
* from MST encoder pre_enable callback.
|
|
|
|
*/
|
2022-01-28 10:37:48 +00:00
|
|
|
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
|
2019-11-06 21:26:36 +00:00
|
|
|
intel_ddi_set_dp_msa(crtc_state, conn_state);
|
2019-08-23 08:20:47 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2016-11-23 14:57:00 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-10-10 12:12:06 +00:00
|
|
|
const struct drm_connector_state *conn_state)
|
2016-09-01 22:08:08 +00:00
|
|
|
{
|
2020-06-26 23:48:32 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
|
2016-09-01 22:08:08 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2012-10-15 18:51:41 +00:00
|
|
|
|
2016-09-01 22:08:08 +00:00
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
|
2021-02-05 21:46:21 +00:00
|
|
|
intel_ddi_enable_clock(encoder, crtc_state);
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2020-11-30 21:21:55 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
|
|
|
|
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain);
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2019-09-26 21:06:56 +00:00
|
|
|
icl_program_mg_dp_mode(dig_port, crtc_state);
|
2018-11-02 19:26:55 +00:00
|
|
|
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
|
2018-06-13 17:07:09 +00:00
|
|
|
|
2020-06-26 23:48:32 +00:00
|
|
|
dig_port->set_infoframes(encoder,
|
|
|
|
crtc_state->has_infoframe,
|
|
|
|
crtc_state, conn_state);
|
2016-09-01 22:08:08 +00:00
|
|
|
}
|
2016-07-12 12:59:33 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_pre_enable(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:06 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2017-08-18 13:49:58 +00:00
|
|
|
const struct drm_connector_state *conn_state)
|
2016-09-01 22:08:08 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
2017-10-10 12:12:06 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
|
|
enum pipe pipe = crtc->pipe;
|
2014-04-24 21:54:58 +00:00
|
|
|
|
2017-10-27 19:31:27 +00:00
|
|
|
/*
|
|
|
|
* When called from DP MST code:
|
|
|
|
* - conn_state will be NULL
|
|
|
|
* - encoder will be the main encoder (ie. mst->primary)
|
|
|
|
* - the main connector associated with this port
|
|
|
|
* won't be active or linked to a crtc
|
|
|
|
* - crtc_state will be the state of the first stream to
|
|
|
|
* be activated on this port, and it may not be the same
|
|
|
|
* stream that will be deactivated last, but each stream
|
|
|
|
* should have a state that is identical when it comes to
|
|
|
|
* the DP link parameteres
|
|
|
|
*/
|
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
|
2017-10-05 10:52:12 +00:00
|
|
|
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
|
|
|
|
|
2018-10-12 06:23:11 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
|
|
|
|
conn_state);
|
2018-10-12 06:23:11 +00:00
|
|
|
} else {
|
2020-09-04 11:53:38 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2018-10-12 06:23:11 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_pre_enable_dp(state, encoder, crtc_state,
|
|
|
|
conn_state);
|
2018-10-12 06:23:11 +00:00
|
|
|
|
2020-09-04 11:53:38 +00:00
|
|
|
/* FIXME precompute everything properly */
|
2021-06-10 19:45:27 +00:00
|
|
|
/* FIXME how do we turn infoframes off again? */
|
2023-05-30 09:08:16 +00:00
|
|
|
if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
|
2018-10-12 06:23:11 +00:00
|
|
|
dig_port->set_infoframes(encoder,
|
|
|
|
crtc_state->has_infoframe,
|
|
|
|
crtc_state, conn_state);
|
|
|
|
}
|
2012-10-05 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
static void
|
|
|
|
mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
|
|
|
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
|
|
|
|
XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
|
|
|
|
|
|
|
|
if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
|
|
|
|
XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
|
|
|
|
drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mtl_disable_ddi_buf(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
/* 3.b Clear DDI_CTL_DE Enable to 0. */
|
|
|
|
val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
|
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
|
|
|
|
|
|
|
|
/* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */
|
|
|
|
mtl_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 3.d Disable D2D Link */
|
|
|
|
mtl_ddi_disable_d2d_link(encoder);
|
|
|
|
|
|
|
|
/* 3.e Disable DP_TP_CTL */
|
|
|
|
if (intel_crtc_has_dp_encoder(crtc_state)) {
|
|
|
|
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
|
|
|
|
DP_TP_CTL_ENABLE, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void disable_ddi_buf(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2017-10-10 12:12:01 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2017-10-10 12:12:01 +00:00
|
|
|
bool wait = false;
|
|
|
|
u32 val;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
|
2017-10-10 12:12:01 +00:00
|
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
|
2017-10-10 12:12:01 +00:00
|
|
|
wait = true;
|
|
|
|
}
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
if (intel_crtc_has_dp_encoder(crtc_state))
|
|
|
|
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
|
2023-03-08 21:26:26 +00:00
|
|
|
DP_TP_CTL_ENABLE, 0);
|
2017-10-10 12:12:01 +00:00
|
|
|
|
2018-11-28 20:26:28 +00:00
|
|
|
/* Disable FEC in DP Sink */
|
|
|
|
intel_ddi_disable_fec_state(encoder, crtc_state);
|
|
|
|
|
2017-10-10 12:12:01 +00:00
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
static void intel_disable_ddi_buf(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 14) {
|
|
|
|
mtl_disable_ddi_buf(encoder, crtc_state);
|
|
|
|
|
|
|
|
/* 3.f Disable DP_TP_CTL FEC Enable if it is needed */
|
|
|
|
intel_ddi_disable_fec_state(encoder, crtc_state);
|
|
|
|
} else {
|
|
|
|
disable_ddi_buf(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:03 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2012-10-05 15:05:58 +00:00
|
|
|
{
|
2017-10-10 12:12:03 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2017-10-10 12:12:03 +00:00
|
|
|
struct intel_dp *intel_dp = &dig_port->dp;
|
2023-04-13 21:24:40 +00:00
|
|
|
intel_wakeref_t wakeref;
|
2018-04-07 01:10:53 +00:00
|
|
|
bool is_mst = intel_crtc_has_type(old_crtc_state,
|
|
|
|
INTEL_OUTPUT_DP_MST);
|
2012-10-05 15:06:00 +00:00
|
|
|
|
2020-06-09 22:06:16 +00:00
|
|
|
if (!is_mst)
|
|
|
|
intel_dp_set_infoframes(encoder, false,
|
|
|
|
old_crtc_state, old_conn_state);
|
2020-05-14 06:07:30 +00:00
|
|
|
|
2019-12-02 22:25:13 +00:00
|
|
|
/*
|
|
|
|
* Power down sink before disabling the port, otherwise we end
|
|
|
|
* up getting interrupts from the sink on detecting link loss.
|
|
|
|
*/
|
2020-10-16 19:48:00 +00:00
|
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
|
2019-12-02 22:25:13 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
2019-12-23 01:06:51 +00:00
|
|
|
if (is_mst) {
|
|
|
|
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
|
|
|
|
TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
|
|
|
|
0);
|
2019-12-23 01:06:51 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!is_mst)
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_disable_transcoder_clock(old_crtc_state);
|
2019-12-23 01:06:51 +00:00
|
|
|
}
|
2017-08-22 14:09:14 +00:00
|
|
|
|
2018-11-28 20:26:28 +00:00
|
|
|
intel_disable_ddi_buf(encoder, old_crtc_state);
|
2017-05-31 17:05:35 +00:00
|
|
|
|
2019-12-05 21:03:49 +00:00
|
|
|
/*
|
|
|
|
* From TGL spec: "If single stream or multi-stream master transcoder:
|
|
|
|
* Configure Transcoder Clock select to direct no clock to the
|
|
|
|
* transcoder"
|
|
|
|
*/
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_disable_transcoder_clock(old_crtc_state);
|
2019-12-05 21:03:49 +00:00
|
|
|
|
2021-01-08 17:44:12 +00:00
|
|
|
intel_pps_vdd_on(intel_dp);
|
|
|
|
intel_pps_off(intel_dp);
|
2012-10-15 18:51:32 +00:00
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
|
|
|
|
|
|
|
|
if (wakeref)
|
2020-11-30 21:21:55 +00:00
|
|
|
intel_display_power_put(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain,
|
2023-04-13 21:24:40 +00:00
|
|
|
wakeref);
|
2017-08-22 14:09:14 +00:00
|
|
|
|
2021-02-05 21:46:21 +00:00
|
|
|
intel_ddi_disable_clock(encoder);
|
2023-04-13 21:24:40 +00:00
|
|
|
|
|
|
|
/* De-select Thunderbolt */
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
|
|
|
|
XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
|
2017-10-10 12:12:03 +00:00
|
|
|
}
|
2017-08-22 14:09:14 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:03 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2017-10-10 12:12:03 +00:00
|
|
|
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
|
2023-04-13 21:24:40 +00:00
|
|
|
intel_wakeref_t wakeref;
|
2012-10-23 20:30:07 +00:00
|
|
|
|
2018-09-20 18:51:36 +00:00
|
|
|
dig_port->set_infoframes(encoder, false,
|
2018-06-13 17:07:09 +00:00
|
|
|
old_crtc_state, old_conn_state);
|
|
|
|
|
2022-06-17 11:28:07 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) < 12)
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_disable_transcoder_clock(old_crtc_state);
|
2018-06-13 17:27:46 +00:00
|
|
|
|
2018-11-28 20:26:28 +00:00
|
|
|
intel_disable_ddi_buf(encoder, old_crtc_state);
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2022-06-17 11:28:07 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2023-02-13 22:52:47 +00:00
|
|
|
intel_ddi_disable_transcoder_clock(old_crtc_state);
|
2022-06-17 11:28:07 +00:00
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
|
|
|
|
if (wakeref)
|
|
|
|
intel_display_power_put(dev_priv,
|
|
|
|
dig_port->ddi_io_power_domain,
|
|
|
|
wakeref);
|
2016-05-02 19:08:24 +00:00
|
|
|
|
2021-02-05 21:46:21 +00:00
|
|
|
intel_ddi_disable_clock(encoder);
|
2017-10-10 12:12:03 +00:00
|
|
|
|
|
|
|
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
|
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_post_disable(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:03 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
2018-11-29 14:12:16 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2022-02-03 18:38:23 +00:00
|
|
|
struct intel_crtc *slave_crtc;
|
2018-11-29 14:12:16 +00:00
|
|
|
|
2020-01-08 14:45:50 +00:00
|
|
|
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
|
|
|
|
intel_crtc_vblank_off(old_crtc_state);
|
2019-12-13 19:52:17 +00:00
|
|
|
|
2022-12-02 13:44:11 +00:00
|
|
|
intel_disable_transcoder(old_crtc_state);
|
|
|
|
|
2020-01-08 14:45:50 +00:00
|
|
|
intel_ddi_disable_transcoder_func(old_crtc_state);
|
2019-12-13 19:52:17 +00:00
|
|
|
|
2020-01-08 14:45:50 +00:00
|
|
|
intel_dsc_disable(old_crtc_state);
|
2019-12-13 19:52:17 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 9)
|
2020-01-08 14:45:50 +00:00
|
|
|
skl_scaler_disable(old_crtc_state);
|
|
|
|
else
|
|
|
|
ilk_pfit_disable(old_crtc_state);
|
|
|
|
}
|
2019-12-13 19:52:17 +00:00
|
|
|
|
2022-02-03 18:38:23 +00:00
|
|
|
for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
|
|
|
|
intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
|
2020-11-17 19:47:08 +00:00
|
|
|
const struct intel_crtc_state *old_slave_crtc_state =
|
2021-10-22 10:32:59 +00:00
|
|
|
intel_atomic_get_old_crtc_state(state, slave_crtc);
|
2020-11-17 19:47:08 +00:00
|
|
|
|
|
|
|
intel_crtc_vblank_off(old_slave_crtc_state);
|
|
|
|
|
|
|
|
intel_dsc_disable(old_slave_crtc_state);
|
|
|
|
skl_scaler_disable(old_slave_crtc_state);
|
|
|
|
}
|
|
|
|
|
2017-10-10 12:12:03 +00:00
|
|
|
/*
|
2017-10-27 19:31:27 +00:00
|
|
|
* When called from DP MST code:
|
|
|
|
* - old_conn_state will be NULL
|
|
|
|
* - encoder will be the main encoder (ie. mst->primary)
|
|
|
|
* - the main connector associated with this port
|
|
|
|
* won't be active or linked to a crtc
|
|
|
|
* - old_crtc_state will be the state of the last stream to
|
|
|
|
* be deactivated on this port, and it may not be the same
|
|
|
|
* stream that was activated last, but each stream
|
|
|
|
* should have a state that is identical when it comes to
|
|
|
|
* the DP link parameteres
|
2017-10-10 12:12:03 +00:00
|
|
|
*/
|
2017-10-27 19:31:27 +00:00
|
|
|
|
|
|
|
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
|
|
|
|
old_conn_state);
|
2017-10-10 12:12:03 +00:00
|
|
|
else
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
|
|
|
|
old_conn_state);
|
2023-03-23 14:20:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
bool is_tc_port = intel_phy_is_tc(i915, phy);
|
2018-11-29 14:12:16 +00:00
|
|
|
|
2022-11-14 12:22:50 +00:00
|
|
|
main_link_aux_power_domain_put(dig_port, old_crtc_state);
|
2019-12-13 19:52:14 +00:00
|
|
|
|
|
|
|
if (is_tc_port)
|
|
|
|
intel_tc_port_put_link(dig_port);
|
2012-10-05 15:05:58 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:31 +00:00
|
|
|
static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
const struct drm_connector_state *conn_state;
|
|
|
|
struct drm_connector *conn;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!crtc_state->sync_mode_slaves_mask)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
|
|
|
|
struct intel_encoder *slave_encoder =
|
|
|
|
to_intel_encoder(conn_state->best_encoder);
|
|
|
|
struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
|
|
|
|
const struct intel_crtc_state *slave_crtc_state;
|
|
|
|
|
|
|
|
if (!slave_crtc)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
slave_crtc_state =
|
|
|
|
intel_atomic_get_new_crtc_state(state, slave_crtc);
|
|
|
|
|
|
|
|
if (slave_crtc_state->master_transcoder !=
|
|
|
|
crtc_state->cpu_transcoder)
|
|
|
|
continue;
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
|
|
|
|
slave_crtc_state);
|
2020-03-13 16:48:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
usleep_range(200, 400);
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_stop_link_train(enc_to_intel_dp(encoder),
|
|
|
|
crtc_state);
|
2020-03-13 16:48:31 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_enable_ddi_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:07 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2012-05-09 18:37:31 +00:00
|
|
|
{
|
2017-10-10 12:12:07 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2020-11-30 20:47:37 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
|
2020-10-01 11:10:53 +00:00
|
|
|
intel_dp_stop_link_train(intel_dp, crtc_state);
|
2012-10-23 20:30:06 +00:00
|
|
|
|
2021-10-05 20:23:22 +00:00
|
|
|
drm_connector_update_privacy_screen(conn_state);
|
2017-10-10 12:12:07 +00:00
|
|
|
intel_edp_backlight_on(crtc_state, conn_state);
|
2020-11-30 20:47:37 +00:00
|
|
|
|
2023-05-30 09:08:16 +00:00
|
|
|
if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp))
|
2020-11-30 20:47:37 +00:00
|
|
|
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
|
|
|
|
|
2022-03-30 09:41:09 +00:00
|
|
|
intel_audio_codec_enable(encoder, crtc_state, conn_state);
|
2020-03-13 16:48:31 +00:00
|
|
|
|
|
|
|
trans_port_sync_stop_link_train(state, encoder, crtc_state);
|
2017-10-10 12:12:07 +00:00
|
|
|
}
|
|
|
|
|
2018-11-19 18:00:21 +00:00
|
|
|
static i915_reg_t
|
|
|
|
gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
2019-10-24 12:21:36 +00:00
|
|
|
static const enum transcoder trans[] = {
|
|
|
|
[PORT_A] = TRANSCODER_EDP,
|
|
|
|
[PORT_B] = TRANSCODER_A,
|
|
|
|
[PORT_C] = TRANSCODER_B,
|
|
|
|
[PORT_D] = TRANSCODER_C,
|
|
|
|
[PORT_E] = TRANSCODER_A,
|
2018-11-19 18:00:21 +00:00
|
|
|
};
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
|
2018-11-19 18:00:21 +00:00
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
|
2018-11-19 18:00:21 +00:00
|
|
|
port = PORT_A;
|
|
|
|
|
2019-10-24 12:21:36 +00:00
|
|
|
return CHICKEN_TRANS(trans[port]);
|
2018-11-19 18:00:21 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:07 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2018-03-22 15:47:07 +00:00
|
|
|
struct drm_connector *connector = conn_state->connector;
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2022-07-26 13:43:13 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, port);
|
|
|
|
u32 buf_ctl;
|
2017-10-10 12:12:07 +00:00
|
|
|
|
2018-03-22 15:47:07 +00:00
|
|
|
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
|
|
|
|
crtc_state->hdmi_high_tmds_clock_ratio,
|
|
|
|
crtc_state->hdmi_scrambling))
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
|
|
|
|
connector->base.id, connector->name);
|
2017-10-10 12:12:07 +00:00
|
|
|
|
2021-10-01 13:00:59 +00:00
|
|
|
if (has_buf_trans_select(dev_priv))
|
2021-10-01 13:01:00 +00:00
|
|
|
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
|
2021-01-28 15:59:47 +00:00
|
|
|
|
2023-04-13 21:24:42 +00:00
|
|
|
/* e. Enable D2D Link for C10/C20 Phy */
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
mtl_ddi_enable_d2d(encoder);
|
|
|
|
|
2021-10-01 13:01:00 +00:00
|
|
|
encoder->set_signal_levels(encoder, crtc_state);
|
2021-01-28 15:59:47 +00:00
|
|
|
|
2018-01-22 17:41:31 +00:00
|
|
|
/* Display WA #1143: skl,kbl,cfl */
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
|
2018-01-22 17:41:31 +00:00
|
|
|
/*
|
|
|
|
* For some reason these chicken bits have been
|
|
|
|
* stuffed into a transcoder register, event though
|
|
|
|
* the bits affect a specific DDI port rather than
|
|
|
|
* a specific transcoder.
|
|
|
|
*/
|
2018-11-19 18:00:21 +00:00
|
|
|
i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
|
2018-01-22 17:41:31 +00:00
|
|
|
u32 val;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
val = intel_de_read(dev_priv, reg);
|
2018-01-22 17:41:31 +00:00
|
|
|
|
|
|
|
if (port == PORT_E)
|
|
|
|
val |= DDIE_TRAINING_OVERRIDE_ENABLE |
|
|
|
|
DDIE_TRAINING_OVERRIDE_VALUE;
|
|
|
|
else
|
|
|
|
val |= DDI_TRAINING_OVERRIDE_ENABLE |
|
|
|
|
DDI_TRAINING_OVERRIDE_VALUE;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, reg, val);
|
|
|
|
intel_de_posting_read(dev_priv, reg);
|
2018-01-22 17:41:31 +00:00
|
|
|
|
|
|
|
udelay(1);
|
|
|
|
|
|
|
|
if (port == PORT_E)
|
|
|
|
val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
|
|
|
|
DDIE_TRAINING_OVERRIDE_VALUE);
|
|
|
|
else
|
|
|
|
val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
|
|
|
|
DDI_TRAINING_OVERRIDE_VALUE);
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, reg, val);
|
2018-01-22 17:41:31 +00:00
|
|
|
}
|
|
|
|
|
2021-01-28 15:59:46 +00:00
|
|
|
intel_ddi_power_up_lanes(encoder, crtc_state);
|
|
|
|
|
2017-10-10 12:12:07 +00:00
|
|
|
/* In HDMI/DVI mode, the port width, and swing/emphasis values
|
|
|
|
* are ignored so nothing special needs to be done besides
|
|
|
|
* enabling the port.
|
2021-05-19 00:06:23 +00:00
|
|
|
*
|
|
|
|
* On ADL_P the PHY link rate and lane count must be programmed but
|
|
|
|
* these are both 0 for HDMI.
|
2023-04-13 21:24:42 +00:00
|
|
|
*
|
|
|
|
* But MTL onwards HDMI2.1 is supported and in TMDS mode this
|
|
|
|
* is filled with lane count, already set in the crtc_state.
|
|
|
|
* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
|
2017-10-10 12:12:07 +00:00
|
|
|
*/
|
2022-07-26 13:43:13 +00:00
|
|
|
buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
|
2023-04-13 21:24:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14) {
|
|
|
|
u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
|
|
|
|
u32 port_buf = 0;
|
|
|
|
|
|
|
|
port_buf |= XELPDP_PORT_WIDTH(lane_count);
|
|
|
|
|
|
|
|
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
|
|
|
|
port_buf |= XELPDP_PORT_REVERSAL;
|
|
|
|
|
|
|
|
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
|
|
|
|
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
|
|
|
|
|
|
|
|
buf_ctl |= DDI_PORT_WIDTH(lane_count);
|
|
|
|
} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
|
2022-07-26 13:43:13 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
|
|
|
|
buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
|
|
|
|
}
|
2023-04-13 21:24:42 +00:00
|
|
|
|
2022-07-26 13:43:13 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
|
2013-01-22 15:25:25 +00:00
|
|
|
|
2022-11-27 05:22:32 +00:00
|
|
|
intel_wait_ddi_buf_active(dev_priv, port);
|
|
|
|
|
2022-03-30 09:41:09 +00:00
|
|
|
intel_audio_codec_enable(encoder, crtc_state, conn_state);
|
2017-10-10 12:12:07 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_enable_ddi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:07 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
2020-04-06 11:27:45 +00:00
|
|
|
drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
|
2020-01-28 16:28:48 +00:00
|
|
|
|
2022-02-03 18:38:19 +00:00
|
|
|
if (!intel_crtc_is_bigjoiner_slave(crtc_state))
|
2020-11-17 19:47:08 +00:00
|
|
|
intel_ddi_enable_transcoder_func(encoder, crtc_state);
|
2020-04-17 13:47:19 +00:00
|
|
|
|
2022-11-21 15:07:18 +00:00
|
|
|
/* Enable/Disable DP2.0 SDP split config before transcoder */
|
|
|
|
intel_audio_sdp_split_update(encoder, crtc_state);
|
|
|
|
|
2021-09-13 14:44:29 +00:00
|
|
|
intel_enable_transcoder(crtc_state);
|
2020-01-28 16:28:48 +00:00
|
|
|
|
|
|
|
intel_crtc_vblank_on(crtc_state);
|
|
|
|
|
2017-10-10 12:12:07 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
|
2017-10-10 12:12:07 +00:00
|
|
|
else
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
|
2018-01-08 19:55:39 +00:00
|
|
|
|
|
|
|
/* Enable hdcp if it's desired */
|
|
|
|
if (conn_state->content_protection ==
|
|
|
|
DRM_MODE_CONTENT_PROTECTION_DESIRED)
|
2023-05-15 10:32:22 +00:00
|
|
|
intel_hdcp_enable(state, encoder, crtc_state, conn_state);
|
2012-06-30 06:59:56 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_disable_ddi_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:05 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
2012-06-30 06:59:56 +00:00
|
|
|
{
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
2012-10-23 20:30:06 +00:00
|
|
|
|
2018-01-17 19:21:49 +00:00
|
|
|
intel_dp->link_trained = false;
|
|
|
|
|
2022-03-30 09:41:09 +00:00
|
|
|
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
|
2021-10-22 10:32:57 +00:00
|
|
|
|
|
|
|
intel_psr_disable(intel_dp, old_crtc_state);
|
2017-10-10 12:12:05 +00:00
|
|
|
intel_edp_backlight_off(old_conn_state);
|
2018-11-28 20:26:17 +00:00
|
|
|
/* Disable the decompression in DP Sink */
|
|
|
|
intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
|
|
|
|
false);
|
2021-01-22 23:26:42 +00:00
|
|
|
/* Disable Ignore_MSA bit in DP Sink */
|
|
|
|
intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
|
|
|
|
false);
|
2017-10-10 12:12:05 +00:00
|
|
|
}
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 11:24:03 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:05 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2018-03-22 15:47:07 +00:00
|
|
|
struct drm_connector *connector = old_conn_state->connector;
|
|
|
|
|
2022-03-30 09:41:09 +00:00
|
|
|
intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
|
2021-10-22 10:32:57 +00:00
|
|
|
|
2018-03-22 15:47:07 +00:00
|
|
|
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
|
|
|
|
false, false))
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&i915->drm,
|
|
|
|
"[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
|
|
|
|
connector->base.id, connector->name);
|
2017-10-10 12:12:05 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_disable_ddi(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2017-10-10 12:12:05 +00:00
|
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
|
|
const struct drm_connector_state *old_conn_state)
|
|
|
|
{
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder));
|
|
|
|
|
2018-01-08 19:55:39 +00:00
|
|
|
intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
|
|
|
|
|
2017-10-10 12:12:05 +00:00
|
|
|
if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
|
|
|
|
old_conn_state);
|
2017-10-10 12:12:05 +00:00
|
|
|
else
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_disable_ddi_dp(state, encoder, old_crtc_state,
|
|
|
|
old_conn_state);
|
2012-05-09 18:37:31 +00:00
|
|
|
}
|
2012-10-05 15:05:52 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2018-12-20 13:21:20 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
|
|
|
{
|
2019-09-19 19:53:05 +00:00
|
|
|
intel_ddi_set_dp_msa(crtc_state, conn_state);
|
2019-03-26 14:25:55 +00:00
|
|
|
|
2020-05-14 06:07:29 +00:00
|
|
|
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
|
2019-01-08 16:08:38 +00:00
|
|
|
|
2021-08-25 11:06:51 +00:00
|
|
|
intel_backlight_update(state, encoder, crtc_state, conn_state);
|
2021-10-05 20:23:22 +00:00
|
|
|
drm_connector_update_privacy_screen(conn_state);
|
2018-12-20 13:21:20 +00:00
|
|
|
}
|
|
|
|
|
2020-08-18 15:38:59 +00:00
|
|
|
void intel_ddi_update_pipe(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2018-12-20 13:21:20 +00:00
|
|
|
{
|
2019-08-01 11:41:15 +00:00
|
|
|
|
2020-08-18 15:38:59 +00:00
|
|
|
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
|
|
|
|
!intel_encoder_is_mst(encoder))
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_update_pipe_dp(state, encoder, crtc_state,
|
|
|
|
conn_state);
|
2019-02-04 15:44:40 +00:00
|
|
|
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
|
2018-12-20 13:21:20 +00:00
|
|
|
}
|
|
|
|
|
2023-04-14 17:38:00 +00:00
|
|
|
void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
struct intel_crtc_state *crtc_state =
|
|
|
|
intel_atomic_get_new_crtc_state(state, crtc);
|
|
|
|
struct intel_crtc *slave_crtc;
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
2023-04-28 09:54:21 +00:00
|
|
|
/* FIXME: Add MTL pll_mgr */
|
|
|
|
if (DISPLAY_VER(i915) >= 14 || !intel_phy_is_tc(i915, phy))
|
2023-04-14 17:38:00 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
intel_update_active_dpll(state, crtc, encoder);
|
|
|
|
for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
|
|
|
|
intel_crtc_bigjoiner_slave_pipes(crtc_state))
|
|
|
|
intel_update_active_dpll(state, slave_crtc, encoder);
|
|
|
|
}
|
|
|
|
|
2018-11-01 14:04:24 +00:00
|
|
|
static void
|
2020-03-13 16:48:30 +00:00
|
|
|
intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
|
|
|
|
struct intel_encoder *encoder,
|
2018-11-01 14:04:24 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct drm_connector_state *conn_state)
|
2018-10-23 19:12:48 +00:00
|
|
|
{
|
2018-11-01 14:04:24 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2019-07-09 18:39:33 +00:00
|
|
|
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
|
|
|
|
bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
|
2018-11-01 14:04:24 +00:00
|
|
|
|
2023-03-23 14:20:35 +00:00
|
|
|
if (is_tc_port) {
|
|
|
|
struct intel_crtc *master_crtc =
|
|
|
|
to_intel_crtc(crtc_state->uapi.crtc);
|
|
|
|
|
2019-06-28 14:36:32 +00:00
|
|
|
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
|
2023-04-14 17:38:00 +00:00
|
|
|
intel_ddi_update_active_dpll(state, encoder, master_crtc);
|
2023-03-23 14:20:35 +00:00
|
|
|
}
|
|
|
|
|
2022-11-14 12:22:50 +00:00
|
|
|
main_link_aux_power_domain_get(dig_port, crtc_state);
|
2018-11-01 14:04:24 +00:00
|
|
|
|
2021-09-21 00:23:05 +00:00
|
|
|
if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
|
2019-07-08 17:28:14 +00:00
|
|
|
/*
|
|
|
|
* Program the lane count for static/dynamic connections on
|
|
|
|
* Type-C ports. Skip this step for TBT.
|
|
|
|
*/
|
|
|
|
intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
|
2021-04-07 20:39:45 +00:00
|
|
|
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
2018-11-01 14:04:24 +00:00
|
|
|
bxt_ddi_phy_set_lane_optim_mask(encoder,
|
|
|
|
crtc_state->lane_lat_optim_mask);
|
|
|
|
}
|
|
|
|
|
2022-02-18 12:26:11 +00:00
|
|
|
static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
|
|
|
|
int ln;
|
|
|
|
|
2022-10-25 11:44:55 +00:00
|
|
|
for (ln = 0; ln < 2; ln++)
|
2022-10-25 11:44:57 +00:00
|
|
|
intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
|
2022-02-18 12:26:11 +00:00
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:40 +00:00
|
|
|
static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *encoder = &dig_port->base;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
u32 dp_tp_ctl;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: To train with only a different voltage swing entry is not
|
|
|
|
* necessary disable and enable port
|
|
|
|
*/
|
|
|
|
dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
|
|
|
if (dp_tp_ctl & DP_TP_CTL_ENABLE)
|
|
|
|
mtl_disable_ddi_buf(encoder, crtc_state);
|
|
|
|
|
|
|
|
/* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
|
|
|
|
dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
|
|
|
|
dp_tp_ctl |= DP_TP_CTL_MODE_MST;
|
|
|
|
} else {
|
|
|
|
dp_tp_ctl |= DP_TP_CTL_MODE_SST;
|
2023-05-03 11:36:59 +00:00
|
|
|
if (crtc_state->enhanced_framing)
|
2023-04-13 21:24:40 +00:00
|
|
|
dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
|
|
|
}
|
|
|
|
intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
|
|
|
|
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
|
|
|
|
|
|
|
/* 6.f Enable D2D Link */
|
|
|
|
mtl_ddi_enable_d2d(encoder);
|
|
|
|
|
|
|
|
/* 6.g Configure voltage swing and related IO settings */
|
|
|
|
encoder->set_signal_levels(encoder, crtc_state);
|
|
|
|
|
|
|
|
/* 6.h Configure PORT_BUF_CTL1 */
|
|
|
|
mtl_port_buf_ctl_program(encoder, crtc_state);
|
|
|
|
|
|
|
|
/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
|
|
|
|
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
|
|
|
|
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
|
|
|
|
|
|
|
|
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
|
|
|
|
intel_wait_ddi_buf_active(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2012-10-15 18:51:41 +00:00
|
|
|
{
|
2022-02-18 12:26:11 +00:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *encoder = &dig_port->base;
|
2020-09-29 23:34:49 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
2019-10-30 01:24:47 +00:00
|
|
|
u32 dp_tp_ctl, ddi_buf_ctl;
|
2013-02-24 22:35:38 +00:00
|
|
|
bool wait = false;
|
2012-10-15 18:51:41 +00:00
|
|
|
|
2020-09-29 23:34:49 +00:00
|
|
|
dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
2019-10-30 01:24:47 +00:00
|
|
|
|
|
|
|
if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
|
2019-10-30 01:24:47 +00:00
|
|
|
if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port),
|
|
|
|
ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
|
2012-10-15 18:51:41 +00:00
|
|
|
wait = true;
|
|
|
|
}
|
|
|
|
|
2023-03-08 21:26:26 +00:00
|
|
|
dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
|
2020-09-29 23:34:49 +00:00
|
|
|
intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
|
|
|
|
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
2012-10-15 18:51:41 +00:00
|
|
|
|
|
|
|
if (wait)
|
|
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
}
|
|
|
|
|
2020-07-14 15:31:40 +00:00
|
|
|
dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
|
2020-10-01 11:10:53 +00:00
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
|
2019-10-30 01:24:47 +00:00
|
|
|
dp_tp_ctl |= DP_TP_CTL_MODE_MST;
|
2020-10-01 11:10:53 +00:00
|
|
|
} else {
|
2019-10-30 01:24:47 +00:00
|
|
|
dp_tp_ctl |= DP_TP_CTL_MODE_SST;
|
2023-05-03 11:36:59 +00:00
|
|
|
if (crtc_state->enhanced_framing)
|
2019-10-30 01:24:47 +00:00
|
|
|
dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
2014-05-02 04:02:48 +00:00
|
|
|
}
|
2020-09-29 23:34:49 +00:00
|
|
|
intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
|
|
|
|
intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
2012-10-15 18:51:41 +00:00
|
|
|
|
2022-02-18 12:26:11 +00:00
|
|
|
if (IS_ALDERLAKE_P(dev_priv) &&
|
|
|
|
(intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
|
|
|
|
adlp_tbt_to_dp_alt_switch_wa(encoder);
|
|
|
|
|
2012-10-15 18:51:41 +00:00
|
|
|
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
|
|
|
|
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
|
2012-10-15 18:51:41 +00:00
|
|
|
|
2020-07-01 22:10:52 +00:00
|
|
|
intel_wait_ddi_buf_active(dev_priv, port);
|
2012-10-15 18:51:41 +00:00
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2020-04-20 20:06:07 +00:00
|
|
|
static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
|
2020-10-01 11:10:53 +00:00
|
|
|
const struct intel_crtc_state *crtc_state,
|
2020-04-20 20:06:07 +00:00
|
|
|
u8 dp_train_pat)
|
|
|
|
{
|
2020-09-29 23:34:49 +00:00
|
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2020-04-20 20:06:07 +00:00
|
|
|
u32 temp;
|
|
|
|
|
2020-09-29 23:34:49 +00:00
|
|
|
temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
|
2020-04-20 20:06:07 +00:00
|
|
|
|
|
|
|
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
|
2020-10-07 17:09:12 +00:00
|
|
|
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
|
2020-04-20 20:06:07 +00:00
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_4:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-09-29 23:34:49 +00:00
|
|
|
intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
|
2020-04-20 20:06:07 +00:00
|
|
|
}
|
|
|
|
|
2020-10-01 11:10:53 +00:00
|
|
|
static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
2020-04-20 20:06:09 +00:00
|
|
|
{
|
|
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum port port = encoder->port;
|
|
|
|
|
2023-01-05 13:10:45 +00:00
|
|
|
intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state),
|
|
|
|
DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
|
2020-04-20 20:06:09 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Until TGL on PORT_A we can have only eDP in SST mode. There the only
|
|
|
|
* reason we need to set idle transmission mode is to work around a HW
|
|
|
|
* issue where we enable the pipe while not in idle link-training mode.
|
|
|
|
* In this case there is requirement to wait for a minimum number of
|
|
|
|
* idle patterns to be sent.
|
|
|
|
*/
|
2021-03-20 04:42:42 +00:00
|
|
|
if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
|
2020-04-20 20:06:09 +00:00
|
|
|
return;
|
|
|
|
|
2020-09-29 23:34:49 +00:00
|
|
|
if (intel_de_wait_for_set(dev_priv,
|
|
|
|
dp_tp_status_reg(encoder, crtc_state),
|
2020-04-20 20:06:09 +00:00
|
|
|
DP_TP_STATUS_IDLE_DONE, 1))
|
|
|
|
drm_err(&dev_priv->drm,
|
|
|
|
"Timed out waiting for DP idle patterns\n");
|
|
|
|
}
|
|
|
|
|
2017-11-29 16:43:03 +00:00
|
|
|
static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder)
|
2016-11-28 12:07:06 +00:00
|
|
|
{
|
2017-11-29 16:43:03 +00:00
|
|
|
if (cpu_transcoder == TRANSCODER_EDP)
|
|
|
|
return false;
|
2016-11-28 12:07:06 +00:00
|
|
|
|
2021-07-29 12:18:58 +00:00
|
|
|
if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
|
2017-11-29 16:43:03 +00:00
|
|
|
return false;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
|
2017-11-29 16:43:03 +00:00
|
|
|
AUDIO_OUTPUT_ENABLE(cpu_transcoder);
|
2016-11-28 12:07:06 +00:00
|
|
|
}
|
|
|
|
|
2017-10-24 09:52:14 +00:00
|
|
|
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
|
2020-02-07 00:14:17 +00:00
|
|
|
crtc_state->min_voltage_level = 2;
|
2023-08-01 13:53:38 +00:00
|
|
|
else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
|
|
|
|
crtc_state->port_clock > 594000)
|
2020-02-07 00:14:16 +00:00
|
|
|
crtc_state->min_voltage_level = 3;
|
2021-03-20 04:42:42 +00:00
|
|
|
else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
|
2018-06-14 22:10:17 +00:00
|
|
|
crtc_state->min_voltage_level = 1;
|
2017-10-24 09:52:14 +00:00
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder)
|
2020-03-13 16:48:22 +00:00
|
|
|
{
|
2020-03-13 16:48:26 +00:00
|
|
|
u32 master_select;
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11) {
|
2020-03-13 16:48:26 +00:00
|
|
|
u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
|
2020-03-13 16:48:22 +00:00
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
|
|
|
|
return INVALID_TRANSCODER;
|
2020-03-13 16:48:22 +00:00
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
|
|
|
|
} else {
|
|
|
|
u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
2020-03-13 16:48:22 +00:00
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
|
|
|
|
return INVALID_TRANSCODER;
|
|
|
|
|
|
|
|
master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
|
|
|
|
}
|
2020-03-13 16:48:22 +00:00
|
|
|
|
|
|
|
if (master_select == 0)
|
|
|
|
return TRANSCODER_EDP;
|
|
|
|
else
|
|
|
|
return master_select - 1;
|
|
|
|
}
|
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
|
2020-03-13 16:48:22 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
|
|
|
u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
|
|
|
|
BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
|
|
|
|
enum transcoder cpu_transcoder;
|
|
|
|
|
|
|
|
crtc_state->master_transcoder =
|
2020-03-13 16:48:26 +00:00
|
|
|
bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
|
2020-03-13 16:48:22 +00:00
|
|
|
|
|
|
|
for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
|
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
intel_wakeref_t trans_wakeref;
|
|
|
|
|
|
|
|
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
|
|
|
|
trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
|
|
|
|
power_domain);
|
|
|
|
|
|
|
|
if (!trans_wakeref)
|
|
|
|
continue;
|
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
|
2020-03-13 16:48:22 +00:00
|
|
|
crtc_state->cpu_transcoder)
|
|
|
|
crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
|
|
|
|
|
|
|
|
intel_display_power_put(dev_priv, power_domain, trans_wakeref);
|
|
|
|
}
|
|
|
|
|
|
|
|
drm_WARN_ON(&dev_priv->drm,
|
|
|
|
crtc_state->master_transcoder != INVALID_TRANSCODER &&
|
|
|
|
crtc_state->sync_mode_slaves_mask);
|
|
|
|
}
|
|
|
|
|
2020-11-17 19:47:09 +00:00
|
|
|
static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
2013-05-15 00:08:26 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2021-06-09 08:56:32 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
2015-01-30 10:17:23 +00:00
|
|
|
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
|
2020-11-30 20:47:34 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2013-05-15 00:08:26 +00:00
|
|
|
u32 temp, flags = 0;
|
|
|
|
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
2013-05-15 00:08:26 +00:00
|
|
|
if (temp & TRANS_DDI_PHSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
|
|
if (temp & TRANS_DDI_PVSYNC)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
|
2019-10-31 11:26:02 +00:00
|
|
|
pipe_config->hw.adjusted_mode.flags |= flags;
|
2013-09-06 20:29:00 +00:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_BPC_MASK) {
|
|
|
|
case TRANS_DDI_BPC_6:
|
|
|
|
pipe_config->pipe_bpp = 18;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_8:
|
|
|
|
pipe_config->pipe_bpp = 24;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_10:
|
|
|
|
pipe_config->pipe_bpp = 30;
|
|
|
|
break;
|
|
|
|
case TRANS_DDI_BPC_12:
|
|
|
|
pipe_config->pipe_bpp = 36;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2013-09-10 14:02:54 +00:00
|
|
|
|
|
|
|
switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
2014-04-24 21:54:47 +00:00
|
|
|
pipe_config->has_hdmi_sink = true;
|
2014-11-20 21:33:59 +00:00
|
|
|
|
2019-02-25 17:41:00 +00:00
|
|
|
pipe_config->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframes_enabled(encoder, pipe_config);
|
|
|
|
|
|
|
|
if (pipe_config->infoframes.enable)
|
2014-11-20 21:33:59 +00:00
|
|
|
pipe_config->has_infoframe = true;
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 11:24:03 +00:00
|
|
|
|
2018-12-10 22:52:54 +00:00
|
|
|
if (temp & TRANS_DDI_HDMI_SCRAMBLING)
|
drm/i915: enable scrambling
Geminilake platform sports a native HDMI 2.0 controller, and is
capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
mendates scrambling for these higher clocks, for reduced RF footprint.
This patch checks if the monitor supports scrambling, and if required,
enables it during the modeset.
V2: Addressed review comments from Ville:
- Do not track scrambling status in DRM layer, track somewhere in
driver like in intel_crtc_state.
- Don't talk to monitor at such a low layer, set monitor scrambling
in intel_enable_ddi() before enabling the port.
V3: Addressed review comments from Jani
- In comments, function names, use "sink" instead of "monitor",
so that the implementation could be close to the language of
HDMI spec.
V4: Addressed review comment from Maarten
- scrambling -> hdmi_scrambling
- high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
V5: Addressed review comments from Ville and Ander
- Do not modifiy the crtc_state after compute_config. Move all
scrambling and tmds_clock_ratio calcutations to compute_config.
- While setting scrambling for source/sink, do not check the
conditions again, just go by the crtc_state flags. This will
simplyfy the condition checks.
V6: Addressed review comments from Ville
- Do not add IS_GLK check in disable/enable function, instead add it
in compute_config, while setting state flags.
- Remove unnecessary paranthesis.
- Simplyfy handle_sink_scrambling function as suggested.
- Add readout code for scrambling status in get_ddi_config and add a
check for the same in pipe_config_compare.
V7: Addressed review comments from Ander/Ville
- No separate function for source scrambling, make it inline
- Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
- Do not add platform check while setting source scrambling
- Use pipe_config instead of crtc->config to set sink scrambling
- To readout scrambling status, Compare with SCRAMBLING_MASK
not any of its bits
- Remove platform check in intel_pipe_config_compare while checking
scrambling status
V8: Fixed mege conflict, Addressed review comments from Ander
- Remove the desciption/comment about scrambling fom the caller, move
it to the function
- Move the IS_GLK check into scrambling function
- Fix alignment
V9: Fixed review comments from Ville, Ander
- Pass the scrambling state variables as bool input to the sink_scrambling
function and let the disable call be unconditional.
- Fix alignments in function calls and debug messages.
- Add kernel doc for function intel_hdmi_handle_sink_scrambling
V10: Rebase
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1489404244-16608-6-git-send-email-shashank.sharma@intel.com
2017-03-13 11:24:03 +00:00
|
|
|
pipe_config->hdmi_scrambling = true;
|
|
|
|
if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
|
|
|
|
pipe_config->hdmi_high_tmds_clock_ratio = true;
|
2020-08-23 22:36:59 +00:00
|
|
|
fallthrough;
|
2013-09-10 14:02:54 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
2017-10-27 19:31:23 +00:00
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
|
2023-04-13 21:24:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14)
|
|
|
|
pipe_config->lane_count =
|
|
|
|
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
|
|
|
|
else
|
|
|
|
pipe_config->lane_count = 4;
|
2016-04-27 12:44:16 +00:00
|
|
|
break;
|
2013-09-10 14:02:54 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
2017-10-27 19:31:23 +00:00
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP)
|
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
|
|
|
|
else
|
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
|
|
|
|
pipe_config->lane_count =
|
|
|
|
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
|
2022-01-28 10:37:42 +00:00
|
|
|
|
2022-01-28 10:37:45 +00:00
|
|
|
intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
|
|
|
|
&pipe_config->dp_m2_n2);
|
2019-09-25 08:21:10 +00:00
|
|
|
|
2023-05-03 11:36:59 +00:00
|
|
|
pipe_config->enhanced_framing =
|
|
|
|
intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
|
|
|
|
2023-05-02 14:39:01 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11)
|
2019-09-25 08:21:10 +00:00
|
|
|
pipe_config->fec_enable =
|
2023-05-02 14:39:01 +00:00
|
|
|
intel_de_read(dev_priv,
|
|
|
|
dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE;
|
2019-09-25 08:21:10 +00:00
|
|
|
|
2023-05-30 09:08:16 +00:00
|
|
|
if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp))
|
2020-11-30 20:47:34 +00:00
|
|
|
pipe_config->infoframes.enable |=
|
|
|
|
intel_lspcon_infoframes_enabled(encoder, pipe_config);
|
|
|
|
else
|
|
|
|
pipe_config->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframes_enabled(encoder, pipe_config);
|
2017-10-27 19:31:23 +00:00
|
|
|
break;
|
2021-09-09 12:52:03 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
|
|
|
|
if (!HAS_DP20(dev_priv)) {
|
|
|
|
/* FDI */
|
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
|
2023-05-03 11:36:59 +00:00
|
|
|
pipe_config->enhanced_framing =
|
|
|
|
intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) &
|
|
|
|
DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
2021-09-09 12:52:03 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
fallthrough; /* 128b/132b */
|
2013-09-10 14:02:54 +00:00
|
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
2017-10-27 19:31:23 +00:00
|
|
|
pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
|
2015-07-06 13:39:15 +00:00
|
|
|
pipe_config->lane_count =
|
|
|
|
((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
|
2019-12-23 01:06:49 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 12)
|
2019-12-23 01:06:49 +00:00
|
|
|
pipe_config->mst_master_transcoder =
|
|
|
|
REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
|
|
|
|
|
2022-01-28 10:37:45 +00:00
|
|
|
intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
|
|
|
|
&pipe_config->dp_m_n);
|
2020-05-14 06:07:26 +00:00
|
|
|
|
|
|
|
pipe_config->infoframes.enable |=
|
|
|
|
intel_hdmi_infoframes_enabled(encoder, pipe_config);
|
2013-09-10 14:02:54 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2020-11-17 19:47:09 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static void intel_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config)
|
2020-11-17 19:47:09 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
|
|
|
|
|
|
|
|
/* XXX: DSI transcoder paranoia */
|
|
|
|
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
|
|
|
|
return;
|
|
|
|
|
2021-10-22 10:33:03 +00:00
|
|
|
intel_ddi_read_func_ctl(encoder, pipe_config);
|
2013-11-18 06:38:16 +00:00
|
|
|
|
2021-03-02 11:02:59 +00:00
|
|
|
intel_ddi_mso_get_config(encoder, pipe_config);
|
|
|
|
|
2016-11-28 12:07:06 +00:00
|
|
|
pipe_config->has_audio =
|
2017-11-29 16:43:03 +00:00
|
|
|
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
|
2014-04-24 21:54:52 +00:00
|
|
|
|
2022-05-10 10:42:29 +00:00
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP)
|
|
|
|
intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
|
2014-01-21 20:42:10 +00:00
|
|
|
|
2021-10-22 10:33:03 +00:00
|
|
|
ddi_dotclock_get(pipe_config);
|
2016-06-13 13:44:35 +00:00
|
|
|
|
2021-04-07 20:39:45 +00:00
|
|
|
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
2016-06-13 13:44:35 +00:00
|
|
|
pipe_config->lane_lat_optim_mask =
|
|
|
|
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
|
2017-10-24 09:52:14 +00:00
|
|
|
|
|
|
|
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
|
2019-02-25 17:41:02 +00:00
|
|
|
|
|
|
|
intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
|
|
|
|
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_AVI,
|
|
|
|
&pipe_config->infoframes.avi);
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_SPD,
|
|
|
|
&pipe_config->infoframes.spd);
|
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_VENDOR,
|
|
|
|
&pipe_config->infoframes.hdmi);
|
2019-05-16 14:10:17 +00:00
|
|
|
intel_read_infoframe(encoder, pipe_config,
|
|
|
|
HDMI_INFOFRAME_TYPE_DRM,
|
|
|
|
&pipe_config->infoframes.drm);
|
2020-03-13 16:48:22 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 8)
|
2020-03-13 16:48:26 +00:00
|
|
|
bdw_get_trans_port_sync_config(pipe_config);
|
2020-05-14 06:07:26 +00:00
|
|
|
|
|
|
|
intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
|
2020-05-14 06:07:27 +00:00
|
|
|
intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
|
2021-04-18 00:21:22 +00:00
|
|
|
|
|
|
|
intel_psr_get_config(encoder, pipe_config);
|
2023-01-24 14:46:21 +00:00
|
|
|
|
|
|
|
intel_audio_codec_get_config(encoder, pipe_config);
|
2013-05-15 00:08:26 +00:00
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
void intel_ddi_get_clock(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
|
|
|
|
struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
|
|
|
|
bool pll_active;
|
|
|
|
|
2021-03-10 19:43:51 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
port_dpll->pll = pll;
|
|
|
|
pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
|
|
|
|
drm_WARN_ON(&i915->drm, !pll_active);
|
|
|
|
|
|
|
|
icl_set_active_port_dpll(crtc_state, port_dpll_id);
|
|
|
|
|
|
|
|
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
|
|
|
|
&crtc_state->dpll_hw_state);
|
|
|
|
}
|
|
|
|
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
static void mtl_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
2023-04-28 09:54:28 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
|
2023-04-28 09:54:28 +00:00
|
|
|
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
|
|
|
|
crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
|
|
|
|
} else if (intel_is_c10phy(i915, phy)) {
|
2023-04-28 09:54:22 +00:00
|
|
|
intel_c10pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10);
|
|
|
|
intel_c10pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c10);
|
2023-04-28 09:54:24 +00:00
|
|
|
crtc_state->port_clock = intel_c10pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10);
|
2023-04-28 09:54:22 +00:00
|
|
|
} else {
|
|
|
|
intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20);
|
2023-04-28 09:54:23 +00:00
|
|
|
intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20);
|
2023-04-28 09:54:24 +00:00
|
|
|
crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20);
|
2023-04-28 09:54:22 +00:00
|
|
|
}
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2021-07-23 17:42:33 +00:00
|
|
|
static void dg2_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
|
|
|
|
crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
|
|
|
|
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2021-02-24 14:42:12 +00:00
|
|
|
static void adls_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void rkl_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dg1_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2023-03-16 13:17:22 +00:00
|
|
|
static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
|
|
|
|
{
|
|
|
|
return pll->info->id == DPLL_ID_ICL_TBTPLL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum icl_port_dpll_id
|
|
|
|
icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
|
|
|
|
|
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return ICL_PORT_DPLL_DEFAULT;
|
|
|
|
|
|
|
|
if (icl_ddi_tc_pll_is_tbt(pll))
|
|
|
|
return ICL_PORT_DPLL_DEFAULT;
|
|
|
|
else
|
|
|
|
return ICL_PORT_DPLL_MG_PHY;
|
|
|
|
}
|
|
|
|
|
|
|
|
enum icl_port_dpll_id
|
|
|
|
intel_ddi_port_pll_type(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
if (!encoder->port_pll_type)
|
|
|
|
return ICL_PORT_DPLL_DEFAULT;
|
|
|
|
|
|
|
|
return encoder->port_pll_type(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2021-03-10 19:43:51 +00:00
|
|
|
static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct intel_shared_dpll *pll)
|
2021-02-24 14:42:12 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum icl_port_dpll_id port_dpll_id;
|
|
|
|
struct icl_port_dpll *port_dpll;
|
|
|
|
bool pll_active;
|
|
|
|
|
2021-03-10 19:43:51 +00:00
|
|
|
if (drm_WARN_ON(&i915->drm, !pll))
|
|
|
|
return;
|
2021-02-24 14:42:12 +00:00
|
|
|
|
2023-03-16 13:17:22 +00:00
|
|
|
if (icl_ddi_tc_pll_is_tbt(pll))
|
2021-02-24 14:42:12 +00:00
|
|
|
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
|
|
|
|
else
|
|
|
|
port_dpll_id = ICL_PORT_DPLL_MG_PHY;
|
|
|
|
|
|
|
|
port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
|
|
|
|
|
|
|
|
port_dpll->pll = pll;
|
|
|
|
pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
|
|
|
|
drm_WARN_ON(&i915->drm, !pll_active);
|
|
|
|
|
|
|
|
icl_set_active_port_dpll(crtc_state, port_dpll_id);
|
|
|
|
|
2023-03-16 13:17:22 +00:00
|
|
|
if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
|
2021-02-24 14:42:12 +00:00
|
|
|
crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
|
|
|
|
else
|
|
|
|
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
|
|
|
|
&crtc_state->dpll_hw_state);
|
2021-03-10 19:43:51 +00:00
|
|
|
}
|
2021-02-24 14:42:12 +00:00
|
|
|
|
2021-03-10 19:43:51 +00:00
|
|
|
static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
|
2021-02-24 14:42:12 +00:00
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bxt_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
void hsw_ddi_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
|
|
|
intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
|
|
|
|
intel_ddi_get_config(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2020-10-05 23:01:54 +00:00
|
|
|
static void intel_ddi_sync_state(struct intel_encoder *encoder,
|
|
|
|
const struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
2021-09-29 13:28:27 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
|
|
|
if (intel_phy_is_tc(i915, phy))
|
2023-03-21 22:01:00 +00:00
|
|
|
intel_tc_port_sanitize_mode(enc_to_dig_port(encoder),
|
|
|
|
crtc_state);
|
2021-09-29 13:28:27 +00:00
|
|
|
|
|
|
|
if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
|
2020-10-05 23:01:54 +00:00
|
|
|
intel_dp_sync_state(encoder, crtc_state);
|
|
|
|
}
|
|
|
|
|
2020-10-05 21:53:10 +00:00
|
|
|
static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state)
|
|
|
|
{
|
2022-09-22 19:12:36 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
bool fastset = true;
|
2020-10-05 21:53:10 +00:00
|
|
|
|
2022-09-22 19:12:36 +00:00
|
|
|
if (intel_phy_is_tc(i915, phy)) {
|
|
|
|
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
|
|
|
|
encoder->base.base.id, encoder->base.name);
|
|
|
|
crtc_state->uapi.mode_changed = true;
|
|
|
|
fastset = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_crtc_has_dp_encoder(crtc_state) &&
|
|
|
|
!intel_dp_initial_fastset_check(encoder, crtc_state))
|
|
|
|
fastset = false;
|
|
|
|
|
|
|
|
return fastset;
|
2020-10-05 21:53:10 +00:00
|
|
|
}
|
|
|
|
|
2017-10-27 19:31:24 +00:00
|
|
|
static enum intel_output_type
|
|
|
|
intel_ddi_compute_output_type(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
|
|
|
switch (conn_state->connector->connector_type) {
|
|
|
|
case DRM_MODE_CONNECTOR_HDMIA:
|
|
|
|
return INTEL_OUTPUT_HDMI;
|
|
|
|
case DRM_MODE_CONNECTOR_eDP:
|
|
|
|
return INTEL_OUTPUT_EDP;
|
|
|
|
case DRM_MODE_CONNECTOR_DisplayPort:
|
|
|
|
return INTEL_OUTPUT_DP;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(conn_state->connector->connector_type);
|
|
|
|
return INTEL_OUTPUT_UNUSED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-01-15 20:08:00 +00:00
|
|
|
static int intel_ddi_compute_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *pipe_config,
|
|
|
|
struct drm_connector_state *conn_state)
|
2012-10-26 21:05:52 +00:00
|
|
|
{
|
2019-10-31 11:26:03 +00:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2017-10-27 19:31:25 +00:00
|
|
|
enum port port = encoder->port;
|
2016-06-13 13:44:35 +00:00
|
|
|
int ret;
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2020-03-18 17:02:35 +00:00
|
|
|
if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
|
2013-05-21 22:50:22 +00:00
|
|
|
pipe_config->cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
|
2019-10-03 08:17:36 +00:00
|
|
|
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
|
2022-11-07 19:46:03 +00:00
|
|
|
pipe_config->has_hdmi_sink =
|
|
|
|
intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state);
|
|
|
|
|
2016-08-09 15:04:05 +00:00
|
|
|
ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
|
2019-10-03 08:17:36 +00:00
|
|
|
} else {
|
2016-08-09 15:04:05 +00:00
|
|
|
ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
|
2019-10-03 08:17:36 +00:00
|
|
|
}
|
|
|
|
|
2019-04-11 16:49:25 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-06-13 13:44:35 +00:00
|
|
|
|
2019-04-25 16:29:06 +00:00
|
|
|
if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
|
|
|
|
pipe_config->cpu_transcoder == TRANSCODER_EDP)
|
|
|
|
pipe_config->pch_pfit.force_thru =
|
|
|
|
pipe_config->pch_pfit.enabled ||
|
|
|
|
pipe_config->crc_enabled;
|
|
|
|
|
2021-04-07 20:39:45 +00:00
|
|
|
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
2016-06-13 13:44:35 +00:00
|
|
|
pipe_config->lane_lat_optim_mask =
|
2017-10-27 13:43:48 +00:00
|
|
|
bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
|
2016-06-13 13:44:35 +00:00
|
|
|
|
2017-10-24 09:52:14 +00:00
|
|
|
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
|
|
|
|
|
2019-04-11 16:49:25 +00:00
|
|
|
return 0;
|
2012-10-26 21:05:52 +00:00
|
|
|
}
|
|
|
|
|
2020-02-14 11:41:25 +00:00
|
|
|
static bool mode_equal(const struct drm_display_mode *mode1,
|
|
|
|
const struct drm_display_mode *mode2)
|
|
|
|
{
|
|
|
|
return drm_mode_match(mode1, mode2,
|
|
|
|
DRM_MODE_MATCH_TIMINGS |
|
|
|
|
DRM_MODE_MATCH_FLAGS |
|
|
|
|
DRM_MODE_MATCH_3D_FLAGS) &&
|
|
|
|
mode1->clock == mode2->clock; /* we want an exact match */
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool m_n_equal(const struct intel_link_m_n *m_n_1,
|
|
|
|
const struct intel_link_m_n *m_n_2)
|
|
|
|
{
|
|
|
|
return m_n_1->tu == m_n_2->tu &&
|
2022-01-27 09:32:52 +00:00
|
|
|
m_n_1->data_m == m_n_2->data_m &&
|
|
|
|
m_n_1->data_n == m_n_2->data_n &&
|
2020-02-14 11:41:25 +00:00
|
|
|
m_n_1->link_m == m_n_2->link_m &&
|
|
|
|
m_n_1->link_n == m_n_2->link_n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
|
|
|
|
const struct intel_crtc_state *crtc_state2)
|
|
|
|
{
|
2024-04-04 21:34:27 +00:00
|
|
|
/*
|
|
|
|
* FIXME the modeset sequence is currently wrong and
|
|
|
|
* can't deal with bigjoiner + port sync at the same time.
|
|
|
|
*/
|
2020-02-14 11:41:25 +00:00
|
|
|
return crtc_state1->hw.active && crtc_state2->hw.active &&
|
2024-04-04 21:34:27 +00:00
|
|
|
!crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes &&
|
2020-02-14 11:41:25 +00:00
|
|
|
crtc_state1->output_types == crtc_state2->output_types &&
|
|
|
|
crtc_state1->output_format == crtc_state2->output_format &&
|
|
|
|
crtc_state1->lane_count == crtc_state2->lane_count &&
|
|
|
|
crtc_state1->port_clock == crtc_state2->port_clock &&
|
|
|
|
mode_equal(&crtc_state1->hw.adjusted_mode,
|
|
|
|
&crtc_state2->hw.adjusted_mode) &&
|
|
|
|
m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u8
|
|
|
|
intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
|
|
|
|
int tile_group_id)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector;
|
|
|
|
const struct drm_connector_state *conn_state;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
|
|
|
|
struct intel_atomic_state *state =
|
|
|
|
to_intel_atomic_state(ref_crtc_state->uapi.state);
|
|
|
|
u8 transcoders = 0;
|
|
|
|
int i;
|
|
|
|
|
2020-03-13 16:48:26 +00:00
|
|
|
/*
|
|
|
|
* We don't enable port sync on BDW due to missing w/as and
|
|
|
|
* due to not having adjusted the modeset sequence appropriately.
|
|
|
|
*/
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) < 9)
|
2020-02-14 11:41:25 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
|
|
|
|
const struct intel_crtc_state *crtc_state;
|
|
|
|
|
|
|
|
if (!crtc)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!connector->has_tile ||
|
|
|
|
connector->tile_group->id !=
|
|
|
|
tile_group_id)
|
|
|
|
continue;
|
|
|
|
crtc_state = intel_atomic_get_new_crtc_state(state,
|
|
|
|
crtc);
|
|
|
|
if (!crtcs_port_sync_compatible(ref_crtc_state,
|
|
|
|
crtc_state))
|
|
|
|
continue;
|
|
|
|
transcoders |= BIT(crtc_state->cpu_transcoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
return transcoders;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_state *crtc_state,
|
|
|
|
struct drm_connector_state *conn_state)
|
|
|
|
{
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2020-02-14 11:41:25 +00:00
|
|
|
struct drm_connector *connector = conn_state->connector;
|
|
|
|
u8 port_sync_transcoders = 0;
|
|
|
|
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
|
|
|
|
encoder->base.base.id, encoder->base.name,
|
|
|
|
crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
|
2020-02-14 11:41:25 +00:00
|
|
|
|
|
|
|
if (connector->has_tile)
|
|
|
|
port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
|
|
|
|
connector->tile_group->id);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* EDP Transcoders cannot be ensalved
|
|
|
|
* make them a master always when present
|
|
|
|
*/
|
|
|
|
if (port_sync_transcoders & BIT(TRANSCODER_EDP))
|
|
|
|
crtc_state->master_transcoder = TRANSCODER_EDP;
|
|
|
|
else
|
|
|
|
crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
|
|
|
|
|
|
|
|
if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
|
|
|
|
crtc_state->master_transcoder = INVALID_TRANSCODER;
|
|
|
|
crtc_state->sync_mode_slaves_mask =
|
|
|
|
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-12-14 18:27:02 +00:00
|
|
|
static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
|
|
|
|
{
|
2021-05-26 14:37:27 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
|
2021-09-29 13:28:32 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
|
2018-12-14 18:27:02 +00:00
|
|
|
|
|
|
|
intel_dp_encoder_flush_work(encoder);
|
2021-09-29 13:28:32 +00:00
|
|
|
if (intel_phy_is_tc(i915, phy))
|
2023-03-23 14:20:13 +00:00
|
|
|
intel_tc_port_cleanup(dig_port);
|
2021-05-26 14:37:27 +00:00
|
|
|
intel_display_power_flush_work(i915);
|
2018-12-14 18:27:02 +00:00
|
|
|
|
|
|
|
drm_encoder_cleanup(encoder);
|
2021-10-04 10:37:37 +00:00
|
|
|
kfree(dig_port->hdcp_port_data.streams);
|
2018-12-14 18:27:02 +00:00
|
|
|
kfree(dig_port);
|
|
|
|
}
|
|
|
|
|
2021-03-18 16:10:12 +00:00
|
|
|
static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
|
|
|
|
{
|
2022-09-22 17:21:48 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->dev);
|
2021-03-18 16:10:12 +00:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
|
2022-09-22 17:21:48 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
|
|
|
|
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
|
2021-03-18 16:10:12 +00:00
|
|
|
|
|
|
|
intel_dp->reset_link_params = true;
|
|
|
|
|
|
|
|
intel_pps_encoder_reset(intel_dp);
|
2022-09-22 17:21:48 +00:00
|
|
|
|
|
|
|
if (intel_phy_is_tc(i915, phy))
|
|
|
|
intel_tc_port_init_mode(dig_port);
|
2021-03-18 16:10:12 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
|
|
|
|
{
|
|
|
|
struct intel_encoder *encoder = to_intel_encoder(_encoder);
|
|
|
|
|
|
|
|
intel_tc_port_link_reset(enc_to_dig_port(encoder));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-26 21:05:52 +00:00
|
|
|
static const struct drm_encoder_funcs intel_ddi_funcs = {
|
2021-03-18 16:10:12 +00:00
|
|
|
.reset = intel_ddi_encoder_reset,
|
2018-12-14 18:27:02 +00:00
|
|
|
.destroy = intel_ddi_encoder_destroy,
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
.late_register = intel_ddi_encoder_late_register,
|
2012-10-26 21:05:52 +00:00
|
|
|
};
|
|
|
|
|
2013-10-09 16:52:36 +00:00
|
|
|
static struct intel_connector *
|
2020-07-01 04:50:54 +00:00
|
|
|
intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
|
2013-10-09 16:52:36 +00:00
|
|
|
{
|
2023-04-13 21:24:40 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
|
2013-10-09 16:52:36 +00:00
|
|
|
struct intel_connector *connector;
|
2020-07-01 04:50:54 +00:00
|
|
|
enum port port = dig_port->base.port;
|
2013-10-09 16:52:36 +00:00
|
|
|
|
2015-04-10 07:59:10 +00:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-09 16:52:36 +00:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->dp.output_reg = DDI_BUF_CTL(port);
|
2023-04-13 21:24:40 +00:00
|
|
|
if (DISPLAY_VER(i915) >= 14)
|
|
|
|
dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
|
|
|
|
else
|
|
|
|
dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->dp.set_link_train = intel_ddi_set_link_train;
|
|
|
|
dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
|
2020-04-20 20:06:07 +00:00
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
|
|
|
|
dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
|
2020-05-12 17:41:42 +00:00
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
if (!intel_dp_init_connector(dig_port, connector)) {
|
2013-10-09 16:52:36 +00:00
|
|
|
kfree(connector);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2021-10-05 20:23:22 +00:00
|
|
|
if (dig_port->base.type == INTEL_OUTPUT_EDP) {
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
|
|
|
struct drm_privacy_screen *privacy_screen;
|
|
|
|
|
|
|
|
privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
|
|
|
|
if (!IS_ERR(privacy_screen)) {
|
|
|
|
drm_connector_attach_privacy_screen_provider(&connector->base,
|
|
|
|
privacy_screen);
|
|
|
|
} else if (PTR_ERR(privacy_screen) != -ENODEV) {
|
|
|
|
drm_warn(dev, "Error getting privacy-screen\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-09 16:52:36 +00:00
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
2018-01-17 19:21:46 +00:00
|
|
|
static int modeset_pipe(struct drm_crtc *crtc,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
|
|
{
|
|
|
|
struct drm_atomic_state *state;
|
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
state = drm_atomic_state_alloc(crtc->dev);
|
|
|
|
if (!state)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
state->acquire_ctx = ctx;
|
2023-03-28 12:23:57 +00:00
|
|
|
to_intel_atomic_state(state)->internal = true;
|
2018-01-17 19:21:46 +00:00
|
|
|
|
|
|
|
crtc_state = drm_atomic_get_crtc_state(state, crtc);
|
|
|
|
if (IS_ERR(crtc_state)) {
|
|
|
|
ret = PTR_ERR(crtc_state);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2019-03-02 00:33:49 +00:00
|
|
|
crtc_state->connectors_changed = true;
|
2018-01-17 19:21:46 +00:00
|
|
|
|
|
|
|
ret = drm_atomic_commit(state);
|
2019-03-02 00:33:47 +00:00
|
|
|
out:
|
2018-01-17 19:21:46 +00:00
|
|
|
drm_atomic_state_put(state);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_reset_link(struct intel_encoder *encoder,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
|
2018-01-17 19:21:46 +00:00
|
|
|
struct intel_connector *connector = hdmi->attached_connector;
|
|
|
|
struct i2c_adapter *adapter =
|
|
|
|
intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
|
|
|
|
struct drm_connector_state *conn_state;
|
|
|
|
struct intel_crtc_state *crtc_state;
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
u8 config;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!connector || connector->base.status != connector_status_connected)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
|
|
|
|
ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
conn_state = connector->base.state;
|
|
|
|
|
|
|
|
crtc = to_intel_crtc(conn_state->crtc);
|
|
|
|
if (!crtc)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = drm_modeset_lock(&crtc->base.mutex, ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
crtc_state = to_intel_crtc_state(crtc->base.state);
|
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm,
|
|
|
|
!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
|
2018-01-17 19:21:46 +00:00
|
|
|
|
2019-10-31 11:26:02 +00:00
|
|
|
if (!crtc_state->hw.active)
|
2018-01-17 19:21:46 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!crtc_state->hdmi_high_tmds_clock_ratio &&
|
|
|
|
!crtc_state->hdmi_scrambling)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (conn_state->commit &&
|
|
|
|
!try_wait_for_completion(&conn_state->commit->hw_done))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
|
|
|
|
if (ret < 0) {
|
2023-04-03 22:36:52 +00:00
|
|
|
drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
|
|
|
|
connector->base.base.id, connector->base.name, ret);
|
2018-01-17 19:21:46 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
|
|
|
|
crtc_state->hdmi_high_tmds_clock_ratio &&
|
|
|
|
!!(config & SCDC_SCRAMBLING_ENABLE) ==
|
|
|
|
crtc_state->hdmi_scrambling)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* HDMI 2.0 says that one should not send scrambled data
|
|
|
|
* prior to configuring the sink scrambling, and that
|
|
|
|
* TMDS clock/data transmission should be suspended when
|
|
|
|
* changing the TMDS clock rate in the sink. So let's
|
|
|
|
* just do a full modeset here, even though some sinks
|
|
|
|
* would be perfectly happy if were to just reconfigure
|
|
|
|
* the SCDC settings on the fly.
|
|
|
|
*/
|
|
|
|
return modeset_pipe(&crtc->base, ctx);
|
|
|
|
}
|
|
|
|
|
2019-07-12 00:53:42 +00:00
|
|
|
static enum intel_hotplug_state
|
|
|
|
intel_ddi_hotplug(struct intel_encoder *encoder,
|
2020-03-30 09:54:24 +00:00
|
|
|
struct intel_connector *connector)
|
2018-01-17 19:21:46 +00:00
|
|
|
{
|
2020-03-30 09:54:25 +00:00
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
2019-12-04 18:05:43 +00:00
|
|
|
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
|
2021-01-14 20:50:45 +00:00
|
|
|
struct intel_dp *intel_dp = &dig_port->dp;
|
2020-03-30 09:54:25 +00:00
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
bool is_tc = intel_phy_is_tc(i915, phy);
|
2018-01-17 19:21:46 +00:00
|
|
|
struct drm_modeset_acquire_ctx ctx;
|
2019-07-12 00:53:42 +00:00
|
|
|
enum intel_hotplug_state state;
|
2018-01-17 19:21:46 +00:00
|
|
|
int ret;
|
|
|
|
|
2021-01-14 20:50:45 +00:00
|
|
|
if (intel_dp->compliance.test_active &&
|
|
|
|
intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
|
|
|
|
intel_dp_phy_test(encoder);
|
|
|
|
/* just do the PHY test and nothing else */
|
|
|
|
return INTEL_HOTPLUG_UNCHANGED;
|
|
|
|
}
|
|
|
|
|
2020-03-30 09:54:24 +00:00
|
|
|
state = intel_encoder_hotplug(encoder, connector);
|
2018-01-17 19:21:46 +00:00
|
|
|
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
if (!intel_tc_port_link_reset(dig_port)) {
|
|
|
|
intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) {
|
|
|
|
if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
|
|
|
|
ret = intel_hdmi_reset_link(encoder, &ctx);
|
|
|
|
else
|
|
|
|
ret = intel_dp_retrain_link(encoder, &ctx);
|
|
|
|
}
|
2018-01-17 19:21:46 +00:00
|
|
|
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
drm_WARN_ON(encoder->base.dev, ret);
|
|
|
|
}
|
2018-01-17 19:21:46 +00:00
|
|
|
|
2019-07-12 00:53:43 +00:00
|
|
|
/*
|
|
|
|
* Unpowered type-c dongles can take some time to boot and be
|
|
|
|
* responsible, so here giving some time to those dongles to power up
|
|
|
|
* and then retrying the probe.
|
|
|
|
*
|
|
|
|
* On many platforms the HDMI live state signal is known to be
|
|
|
|
* unreliable, so we can't use it to detect if a sink is connected or
|
|
|
|
* not. Instead we detect if it's connected based on whether we can
|
|
|
|
* read the EDID or not. That in turn has a problem during disconnect,
|
|
|
|
* since the HPD interrupt may be raised before the DDC lines get
|
|
|
|
* disconnected (due to how the required length of DDC vs. HPD
|
|
|
|
* connector pins are specified) and so we'll still be able to get a
|
|
|
|
* valid EDID. To solve this schedule another detection cycle if this
|
|
|
|
* time around we didn't detect any change in the sink's connection
|
|
|
|
* status.
|
2020-03-30 09:54:25 +00:00
|
|
|
*
|
|
|
|
* Type-c connectors which get their HPD signal deasserted then
|
|
|
|
* reasserted, without unplugging/replugging the sink from the
|
|
|
|
* connector, introduce a delay until the AUX channel communication
|
|
|
|
* becomes functional. Retry the detection for 5 seconds on type-c
|
|
|
|
* connectors to account for this delay.
|
2019-07-12 00:53:43 +00:00
|
|
|
*/
|
2020-03-30 09:54:25 +00:00
|
|
|
if (state == INTEL_HOTPLUG_UNCHANGED &&
|
|
|
|
connector->hotplug_retries < (is_tc ? 5 : 1) &&
|
2019-07-12 00:53:43 +00:00
|
|
|
!dig_port->dp.is_mst)
|
|
|
|
state = INTEL_HOTPLUG_RETRY;
|
|
|
|
|
2019-07-12 00:53:42 +00:00
|
|
|
return state;
|
2018-01-17 19:21:46 +00:00
|
|
|
}
|
|
|
|
|
2020-03-11 15:54:20 +00:00
|
|
|
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2022-08-24 13:15:42 +00:00
|
|
|
u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
|
2020-03-11 15:54:20 +00:00
|
|
|
|
|
|
|
return intel_de_read(dev_priv, SDEISR) & bit;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2022-08-24 13:15:42 +00:00
|
|
|
u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
|
2020-03-11 15:54:20 +00:00
|
|
|
|
2020-03-11 15:54:22 +00:00
|
|
|
return intel_de_read(dev_priv, DEISR) & bit;
|
2020-03-11 15:54:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
2022-08-24 13:15:42 +00:00
|
|
|
u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
|
2020-03-11 15:54:20 +00:00
|
|
|
|
|
|
|
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
|
|
|
|
}
|
|
|
|
|
2013-10-09 16:52:36 +00:00
|
|
|
static struct intel_connector *
|
2020-07-01 04:50:54 +00:00
|
|
|
intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
|
2013-10-09 16:52:36 +00:00
|
|
|
{
|
|
|
|
struct intel_connector *connector;
|
2020-07-01 04:50:54 +00:00
|
|
|
enum port port = dig_port->base.port;
|
2013-10-09 16:52:36 +00:00
|
|
|
|
2015-04-10 07:59:10 +00:00
|
|
|
connector = intel_connector_alloc();
|
2013-10-09 16:52:36 +00:00
|
|
|
if (!connector)
|
|
|
|
return NULL;
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
|
|
|
|
intel_hdmi_init_connector(dig_port, connector);
|
2013-10-09 16:52:36 +00:00
|
|
|
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
|
2017-10-23 17:39:20 +00:00
|
|
|
{
|
2020-07-01 04:50:54 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
2017-10-23 17:39:20 +00:00
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
if (dig_port->base.port != PORT_A)
|
2017-10-23 17:39:20 +00:00
|
|
|
return false;
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
if (dig_port->saved_port_bits & DDI_A_4_LANES)
|
2017-10-23 17:39:20 +00:00
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
|
|
|
|
* supported configuration
|
|
|
|
*/
|
2021-04-07 20:39:45 +00:00
|
|
|
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
|
2017-10-23 17:39:20 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-02-06 06:08:55 +00:00
|
|
|
static int
|
2020-07-01 04:50:54 +00:00
|
|
|
intel_ddi_max_lanes(struct intel_digital_port *dig_port)
|
2018-02-06 06:08:55 +00:00
|
|
|
{
|
2020-07-01 04:50:54 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
|
|
|
|
enum port port = dig_port->base.port;
|
2018-02-06 06:08:55 +00:00
|
|
|
int max_lanes = 4;
|
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11)
|
2018-02-06 06:08:55 +00:00
|
|
|
return max_lanes;
|
|
|
|
|
|
|
|
if (port == PORT_A || port == PORT_E) {
|
drm/i915/ddi: use intel_de_*() functions for register access
The implicit "dev_priv" local variable use has been a long-standing pain
point in the register access macros I915_READ(), I915_WRITE(),
POSTING_READ(), I915_READ_FW(), and I915_WRITE_FW().
Replace them with the corresponding new display engine register
accessors intel_de_read(), intel_de_write(), intel_de_posting_read(),
intel_de_read_fw(), and intel_de_write_fw().
No functional changes.
Generated using the following semantic patch:
@@
expression REG, OFFSET;
@@
- I915_READ(REG)
+ intel_de_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- POSTING_READ(REG)
+ intel_de_posting_read(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE(REG, OFFSET)
+ intel_de_write(dev_priv, REG, OFFSET)
@@
expression REG;
@@
- I915_READ_FW(REG)
+ intel_de_read_fw(dev_priv, REG)
@@
expression REG, OFFSET;
@@
- I915_WRITE_FW(REG, OFFSET)
+ intel_de_write_fw(dev_priv, REG, OFFSET)
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2c6050201849484a7f4681ce6e2f69cb7cb26756.1580149467.git.jani.nikula@intel.com
2020-01-27 18:26:05 +00:00
|
|
|
if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
|
2018-02-06 06:08:55 +00:00
|
|
|
max_lanes = port == PORT_A ? 4 : 0;
|
|
|
|
else
|
|
|
|
/* Both A and E share 2 lanes */
|
|
|
|
max_lanes = 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Some BIOS might fail to set this bit on port A if eDP
|
|
|
|
* wasn't lit up at boot. Force this bit set when needed
|
|
|
|
* so we use the proper lane count for our calculations.
|
|
|
|
*/
|
2020-07-01 04:50:54 +00:00
|
|
|
if (intel_ddi_a_force_4_lanes(dig_port)) {
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Forcing DDI_A_4_LANES for port A\n");
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->saved_port_bits |= DDI_A_4_LANES;
|
2018-02-06 06:08:55 +00:00
|
|
|
max_lanes = 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
return max_lanes;
|
|
|
|
}
|
|
|
|
|
2021-05-14 15:36:53 +00:00
|
|
|
static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
if (port >= PORT_D_XELPD)
|
|
|
|
return HPD_PORT_D + port - PORT_D_XELPD;
|
|
|
|
else if (port >= PORT_TC1)
|
|
|
|
return HPD_PORT_TC1 + port - PORT_TC1;
|
|
|
|
else
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
2020-10-21 08:20:29 +00:00
|
|
|
static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
2020-10-28 21:33:06 +00:00
|
|
|
if (port >= PORT_TC1)
|
|
|
|
return HPD_PORT_C + port - PORT_TC1;
|
2020-10-21 08:20:29 +00:00
|
|
|
else
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
2020-06-30 21:55:59 +00:00
|
|
|
static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
2020-10-28 21:33:06 +00:00
|
|
|
if (port >= PORT_TC1)
|
|
|
|
return HPD_PORT_TC1 + port - PORT_TC1;
|
2020-06-30 21:55:59 +00:00
|
|
|
else
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
if (HAS_PCH_TGP(dev_priv))
|
|
|
|
return tgl_hpd_pin(dev_priv, port);
|
|
|
|
|
2020-10-28 21:33:06 +00:00
|
|
|
if (port >= PORT_TC1)
|
|
|
|
return HPD_PORT_C + port - PORT_TC1;
|
2020-06-30 21:55:59 +00:00
|
|
|
else
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
if (port >= PORT_C)
|
|
|
|
return HPD_PORT_TC1 + port - PORT_C;
|
|
|
|
else
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
|
|
|
|
enum port port)
|
|
|
|
{
|
|
|
|
if (port == PORT_D)
|
|
|
|
return HPD_PORT_A;
|
|
|
|
|
2022-06-30 15:05:59 +00:00
|
|
|
if (HAS_PCH_TGP(dev_priv))
|
2020-06-30 21:55:59 +00:00
|
|
|
return icl_hpd_pin(dev_priv, port);
|
|
|
|
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
2021-02-09 19:16:28 +00:00
|
|
|
static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
|
|
|
|
{
|
|
|
|
if (HAS_PCH_TGP(dev_priv))
|
|
|
|
return icl_hpd_pin(dev_priv, port);
|
|
|
|
|
|
|
|
return HPD_PORT_A + port - PORT_A;
|
|
|
|
}
|
|
|
|
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
|
|
|
|
{
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(i915) >= 12)
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
return port >= PORT_TC1;
|
2021-03-20 04:42:42 +00:00
|
|
|
else if (DISPLAY_VER(i915) >= 11)
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
return port >= PORT_C;
|
|
|
|
else
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-06-10 17:42:23 +00:00
|
|
|
static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
intel_dp_encoder_suspend(encoder);
|
2023-05-12 19:55:12 +00:00
|
|
|
}
|
2021-06-10 17:42:23 +00:00
|
|
|
|
2023-05-12 19:55:12 +00:00
|
|
|
static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
2021-06-10 17:42:23 +00:00
|
|
|
|
drm/i915/tc: Reset TypeC PHYs left enabled in DP-alt mode after the sink disconnects
If the output on a DP-alt link with its sink disconnected is kept
enabled for too long (about 20 sec), then some IOM/TCSS firmware timeout
will cause havoc on the PCI bus, at least for other GFX devices on it
which will stop powering up. Since user space is not guaranteed to do a
disabling modeset in time, switch such disconnected but active links to
TBT mode - which is without such shortcomings - with a 2 second delay.
If the above condition is detected already during the driver load/system
resume sanitization step disable the output instead, as at that point no
user space or kernel client depends on a consistent output state yet and
because subsequent atomic modeset on such connectors - without the
actual sink capabilities available - can fail.
An active/disconnected port as above will also block the HPD status of
other active/disconnected ports to get updated (stuck in the connected
state), until the former port is disabled, its PHY is disconnected and
a ~10 ms delay has elapsed. This means the link state for all TypeC
ports/CRTCs must be rechecked after a CRTC is disabled due to the above
reason. For this disconnect the PHY synchronously after the CRTC/port is
disabled and recheck all CRTCs for the above condition whenever such a
port is disabled.
To account for a race condition during driver loading where the sink is
disconnected after the above sanitization step and before the HPD
interrupts get enabled, do an explicit check/link reset if needed from
the encoder's late_register hook, which is called after the HPD
interrupts are enabled already.
v2:
- Handle an active/disconnected port blocking the HPD state update of
another active/disconnected port.
- Cancel the delayed work resetting the link also from the encoder
enable/suspend/shutdown hooks.
- Rebase on the earlier intel_modeset_lock_ctx_retry() addition,
fixing here the missed atomic state reset in case of a retry.
- Fix handling of an error return from intel_atomic_get_crtc_state().
- Recheck if the port needs to be reset after all the atomic state
is locked and async commits are waited on.
v3:
- Add intel_crtc_needs_link_reset(), instead of open-coding it,
keep intel_crtc_has_encoders(). (Ville)
- Fix state dumping and use a bitmask to track disabled CRTCs in
intel_sanitize_all_crtcs(). (Ville)
- Set internal in intel_atomic_state right after allocating it.
(Ville)
- Recheck all CRTCs (not yet force-disabled) after a CRTC is
force-disabled for any reason (not only due to a link state)
in intel_sanitize_all_crtcs().
- Reduce delay after CRTC disabling to 20ms, and use the simpler
msleep().
- Clarify code comment about HPD behaviour in
intel_sanitize_all_crtcs().
- Move all the TC link reset logic to intel_tc.c .
- Cancel the link reset work synchronously during system suspend,
driver unload and shutdown.
v4:
- Rebased on previous patch, which allows calling the TC port
suspend/cleanup handlers without modeset locks held; remove the
display driver suspended assert from the link reset work
accordingly.
v5: (Ville)
- Remove reset work canceling from intel_ddi_pre_pll_enable().
- Track a crtc vs. pipe mask in intel_sanitize_all_crtcs().
- Add reset_link_commit() to clarify the
intel_modeset_lock_ctx_retry loop.
Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5860
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230512195513.2699-2-imre.deak@intel.com
2023-05-12 19:55:13 +00:00
|
|
|
intel_tc_port_suspend(dig_port);
|
2021-06-10 17:42:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
intel_dp_encoder_shutdown(encoder);
|
2021-10-29 19:18:02 +00:00
|
|
|
intel_hdmi_encoder_shutdown(encoder);
|
2023-05-12 19:55:12 +00:00
|
|
|
}
|
2021-06-10 17:42:23 +00:00
|
|
|
|
2023-05-12 19:55:12 +00:00
|
|
|
static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
2021-06-10 17:42:23 +00:00
|
|
|
|
2023-03-23 14:20:13 +00:00
|
|
|
intel_tc_port_cleanup(dig_port);
|
2021-06-10 17:42:23 +00:00
|
|
|
}
|
|
|
|
|
2020-11-17 15:40:28 +00:00
|
|
|
#define port_tc_name(port) ((port) - PORT_TC1 + '1')
|
|
|
|
#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
|
|
|
|
|
2023-06-16 14:08:20 +00:00
|
|
|
static bool port_strap_detected(struct drm_i915_private *i915, enum port port)
|
|
|
|
{
|
|
|
|
/* straps not used on skl+ */
|
|
|
|
if (DISPLAY_VER(i915) >= 9)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
|
|
|
return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
|
|
|
|
case PORT_B:
|
|
|
|
return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
|
|
|
|
case PORT_C:
|
|
|
|
return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
|
|
|
|
case PORT_D:
|
|
|
|
return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
|
|
|
|
case PORT_E:
|
|
|
|
return true; /* no strap for DDI-E */
|
|
|
|
default:
|
|
|
|
MISSING_CASE(port);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-06-30 15:58:42 +00:00
|
|
|
static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
|
|
|
enum phy phy = intel_port_to_phy(i915, encoder->port);
|
|
|
|
|
|
|
|
return init_dp || intel_phy_is_tc(i915, phy);
|
|
|
|
}
|
|
|
|
|
2023-06-30 15:58:46 +00:00
|
|
|
static bool assert_has_icl_dsi(struct drm_i915_private *i915)
|
|
|
|
{
|
|
|
|
return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) &&
|
|
|
|
!IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11,
|
|
|
|
"Platform does not support DSI\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool port_in_use(struct drm_i915_private *i915, enum port port)
|
|
|
|
{
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
|
|
|
|
for_each_intel_encoder(&i915->drm, encoder) {
|
|
|
|
/* FIXME what about second port for dual link DSI? */
|
|
|
|
if (encoder->port == port)
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_ddi_init(struct drm_i915_private *dev_priv,
|
|
|
|
const struct intel_bios_encoder_data *devdata)
|
2012-10-26 21:05:52 +00:00
|
|
|
{
|
2020-07-01 04:50:54 +00:00
|
|
|
struct intel_digital_port *dig_port;
|
2019-11-06 07:17:17 +00:00
|
|
|
struct intel_encoder *encoder;
|
2020-06-10 07:55:10 +00:00
|
|
|
bool init_hdmi, init_dp;
|
2023-06-30 15:58:46 +00:00
|
|
|
enum port port;
|
|
|
|
enum phy phy;
|
|
|
|
|
|
|
|
port = intel_bios_encoder_port(devdata);
|
|
|
|
if (port == PORT_NONE)
|
|
|
|
return;
|
2015-12-08 17:59:37 +00:00
|
|
|
|
2023-06-16 14:08:20 +00:00
|
|
|
if (!port_strap_detected(dev_priv, port)) {
|
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Port %c strap not detected\n", port_name(port));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2023-06-16 14:08:17 +00:00
|
|
|
if (!assert_port_valid(dev_priv, port))
|
|
|
|
return;
|
|
|
|
|
2023-06-30 15:58:46 +00:00
|
|
|
if (port_in_use(dev_priv, port)) {
|
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"Port %c already claimed\n", port_name(port));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_bios_encoder_supports_dsi(devdata)) {
|
|
|
|
/* BXT/GLK handled elsewhere, for now at least */
|
|
|
|
if (!assert_has_icl_dsi(dev_priv))
|
|
|
|
return;
|
|
|
|
|
|
|
|
icl_dsi_init(dev_priv, devdata);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
phy = intel_port_to_phy(dev_priv, port);
|
|
|
|
|
2020-07-16 22:05:50 +00:00
|
|
|
/*
|
|
|
|
* On platforms with HTI (aka HDPORT), if it's enabled at boot it may
|
|
|
|
* have taken over some of the PHYs and made them unavailable to the
|
|
|
|
* driver. In that case we should skip initializing the corresponding
|
|
|
|
* outputs.
|
|
|
|
*/
|
2022-11-09 14:42:06 +00:00
|
|
|
if (intel_hti_uses_phy(dev_priv, phy)) {
|
2020-07-16 22:05:50 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
|
|
|
|
port_name(port), phy_name(phy));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2021-03-17 16:36:51 +00:00
|
|
|
init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
|
|
|
|
intel_bios_encoder_supports_hdmi(devdata);
|
|
|
|
init_dp = intel_bios_encoder_supports_dp(devdata);
|
2016-10-14 14:26:51 +00:00
|
|
|
|
2023-02-08 01:55:01 +00:00
|
|
|
if (intel_bios_encoder_is_lspcon(devdata)) {
|
2016-10-14 14:26:51 +00:00
|
|
|
/*
|
|
|
|
* Lspcon device needs to be driven with DP connector
|
|
|
|
* with special detection sequence. So make sure DP
|
|
|
|
* is initialized before lspcon.
|
|
|
|
*/
|
|
|
|
init_dp = true;
|
|
|
|
init_hdmi = false;
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
|
|
|
|
port_name(port));
|
2016-10-14 14:26:51 +00:00
|
|
|
}
|
|
|
|
|
2013-09-12 20:12:18 +00:00
|
|
|
if (!init_dp && !init_hdmi) {
|
drm/i915/ddi: use struct drm_device based logging
Convert all the DRM_* logging macros to the struct drm_device based
macros to provide device specific logging.
No functional changes.
Generated using the following semantic patch, originally written by
Wambui Karuga <wambui.karugax@gmail.com>, with manual fixups on top:
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_NOTE(
+drm_notice(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Cc: Wambui Karuga <wambui.karugax@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e09bb6e97b2fbc44303acce0523dc35e3e74a456.1584714939.git.jani.nikula@intel.com
2020-03-20 14:36:26 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
|
|
|
|
port_name(port));
|
2015-08-08 00:01:16 +00:00
|
|
|
return;
|
2013-09-12 20:12:18 +00:00
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2022-02-23 16:54:21 +00:00
|
|
|
if (intel_phy_is_snps(dev_priv, phy) &&
|
2023-01-17 14:39:44 +00:00
|
|
|
dev_priv->display.snps.phy_failed_calibration & BIT(phy)) {
|
2022-02-23 16:54:21 +00:00
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
drm/i915/dg2: Do not explode on phy calibration error
When the PHY fails on calibration we were previously skipping the ddi
initialization. However the driver is not really prepared for that,
ultimately leading to a NULL pointer dereference:
[ 75.748348] i915 0000:03:00.0: [drm:intel_modeset_init_nogem [i915]] SNPS PHY A failed to calibrate; output will not be used.
...
[ 75.750336] i915 0000:03:00.0: [drm:intel_modeset_setup_hw_state [i915]] [CRTC:80:pipe A] hw state readout: enabled
...
( no DDI A/PHY A )
[ 75.753080] i915 0000:03:00.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:235:DDI B/PHY B] hw state readout: disabled, pipe A
[ 75.753164] i915 0000:03:00.0: [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:245:DDI C/PHY C] hw state readout: disabled, pipe A
...
[ 75.754425] i915 0000:03:00.0: [drm] *ERROR* crtc 80: Can't calculate constants, dotclock = 0!
[ 75.765558] i915 0000:03:00.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev))
[ 75.765569] WARNING: CPU: 5 PID: 1759 at drivers/gpu/drm/drm_vblank.c:728 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x347/0x360
...
[ 75.781230] BUG: kernel NULL pointer dereference, address: 000000000000007c
[ 75.788198] #PF: supervisor read access in kernel mode
[ 75.793347] #PF: error_code(0x0000) - not-present page
[ 75.798480] PGD 0 P4D 0
[ 75.801019] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ 75.805377] CPU: 5 PID: 1759 Comm: modprobe Tainted: G W 5.18.0-rc1-demarchi+ #199
[ 75.827613] RIP: 0010:icl_aux_power_well_disable+0x3b/0x200 [i915]
[ 75.833890] Code: 83 ec 30 65 48 8b 04 25 28 00 00 00 48 89 44 24 28 48 8b 06 0f b6 70 1c f6 40 20 04 8d 56 fa 0f 45 f2 e8 88 bd ff ff 48 89 ef <8b> 70 7c e8 ed 67 ff ff 48 89 ef 89 c6 e8 73 67 ff ff 84 c0 75 0a
[ 75.852629] RSP: 0018:ffffc90003a7fb30 EFLAGS: 00010246
[ 75.857852] RAX: 0000000000000000 RBX: ffff8881145e8f10 RCX: 0000000000000000
[ 75.864978] RDX: ffff888115220840 RSI: 0000000000000000 RDI: ffff888115220000
[ 75.872106] RBP: ffff888115220000 R08: ffff88888effffe8 R09: 00000000fffdffff
[ 75.879234] R10: ffff88888e200000 R11: ffff88888ed00000 R12: ffff8881145e8f10
[ 75.886363] R13: 0000000000000001 R14: ffff888115223240 R15: 0000000000000000
[ 75.893490] FS: 00007ff6e753a740(0000) GS:ffff88888f680000(0000) knlGS:0000000000000000
[ 75.901573] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 75.907313] CR2: 000000000000007c CR3: 00000001216a6001 CR4: 0000000000770ee0
[ 75.914446] PKRU: 55555554
[ 75.917153] Call Trace:
[ 75.919603] <TASK>
[ 75.921709] intel_power_domains_sanitize_state+0x88/0xb0 [i915]
[ 75.927814] intel_modeset_init_nogem+0x317/0xef0 [i915]
[ 75.933205] i915_driver_probe+0x5f6/0xdf0 [i915]
[ 75.937976] i915_pci_probe+0x51/0x1d0 [i915]
We skip the initialization of PHY A, but later we try to find out what
is the phy for that power well and dereference dig_port, which is NULL.
Failing the PHY calibration could be left as a warning or error, like it
was before commit b4eb76d82a0e ("drm/i915/dg2: Skip output init on PHY
calibration failure"). However that often fails for outputs not being
used, which would make the warning/error appear on systems that have no
visible issues. Anyway, there is still a need to fix those failures,
but that is left for later.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220410061537.4187383-1-lucas.demarchi@intel.com
2022-04-10 06:15:36 +00:00
|
|
|
"SNPS PHY %c failed to calibrate, proceeding anyway\n",
|
2022-02-23 16:54:21 +00:00
|
|
|
phy_name(phy));
|
|
|
|
}
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
|
|
|
|
if (!dig_port)
|
2012-10-26 21:05:52 +00:00
|
|
|
return;
|
|
|
|
|
2023-06-30 15:58:41 +00:00
|
|
|
dig_port->aux_ch = AUX_CH_NONE;
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
encoder = &dig_port->base;
|
2021-03-17 16:36:53 +00:00
|
|
|
encoder->devdata = devdata;
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2021-05-14 15:36:53 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
|
|
|
|
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS,
|
|
|
|
"DDI %c/PHY %c",
|
|
|
|
port_name(port - PORT_D_XELPD + PORT_D),
|
|
|
|
phy_name(phy));
|
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 12) {
|
2020-10-28 21:33:07 +00:00
|
|
|
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
|
|
|
|
|
|
|
|
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS,
|
|
|
|
"DDI %s%c/PHY %s%c",
|
|
|
|
port >= PORT_TC1 ? "TC" : "",
|
2020-11-17 15:40:28 +00:00
|
|
|
port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
|
2020-10-28 21:33:07 +00:00
|
|
|
tc_port != TC_PORT_NONE ? "TC" : "",
|
2020-11-17 15:40:28 +00:00
|
|
|
tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
|
2021-03-20 04:42:42 +00:00
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 11) {
|
2020-10-28 21:33:07 +00:00
|
|
|
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
|
|
|
|
|
|
|
|
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS,
|
|
|
|
"DDI %c%s/PHY %s%c",
|
|
|
|
port_name(port),
|
|
|
|
port >= PORT_C ? " (TC)" : "",
|
|
|
|
tc_port != TC_PORT_NONE ? "TC" : "",
|
2020-11-17 15:40:28 +00:00
|
|
|
tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
|
2020-10-28 21:33:07 +00:00
|
|
|
} else {
|
|
|
|
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS,
|
|
|
|
"DDI %c/PHY %c", port_name(port), phy_name(phy));
|
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2020-08-18 15:38:57 +00:00
|
|
|
mutex_init(&dig_port->hdcp_mutex);
|
|
|
|
dig_port->num_hdcp_streams = 0;
|
|
|
|
|
2019-11-06 07:17:17 +00:00
|
|
|
encoder->hotplug = intel_ddi_hotplug;
|
|
|
|
encoder->compute_output_type = intel_ddi_compute_output_type;
|
|
|
|
encoder->compute_config = intel_ddi_compute_config;
|
2020-02-14 11:41:25 +00:00
|
|
|
encoder->compute_config_late = intel_ddi_compute_config_late;
|
2019-11-06 07:17:17 +00:00
|
|
|
encoder->enable = intel_enable_ddi;
|
|
|
|
encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
|
|
|
|
encoder->pre_enable = intel_ddi_pre_enable;
|
|
|
|
encoder->disable = intel_disable_ddi;
|
2023-03-23 14:20:33 +00:00
|
|
|
encoder->post_pll_disable = intel_ddi_post_pll_disable;
|
2019-11-06 07:17:17 +00:00
|
|
|
encoder->post_disable = intel_ddi_post_disable;
|
|
|
|
encoder->update_pipe = intel_ddi_update_pipe;
|
|
|
|
encoder->get_hw_state = intel_ddi_get_hw_state;
|
2020-10-05 23:01:54 +00:00
|
|
|
encoder->sync_state = intel_ddi_sync_state;
|
2020-10-05 21:53:10 +00:00
|
|
|
encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
|
2021-06-10 17:42:23 +00:00
|
|
|
encoder->suspend = intel_ddi_encoder_suspend;
|
|
|
|
encoder->shutdown = intel_ddi_encoder_shutdown;
|
2019-11-06 07:17:17 +00:00
|
|
|
encoder->get_power_domains = intel_ddi_get_power_domains;
|
|
|
|
|
|
|
|
encoder->type = INTEL_OUTPUT_DDI;
|
2022-04-14 21:06:53 +00:00
|
|
|
encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
|
2019-11-06 07:17:17 +00:00
|
|
|
encoder->port = port;
|
|
|
|
encoder->cloneable = 0;
|
|
|
|
encoder->pipe_mask = ~0;
|
2020-06-30 21:55:59 +00:00
|
|
|
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14) {
|
2023-04-28 09:54:27 +00:00
|
|
|
encoder->enable_clock = intel_mtl_pll_enable;
|
|
|
|
encoder->disable_clock = intel_mtl_pll_disable;
|
2023-04-28 09:54:30 +00:00
|
|
|
encoder->port_pll_type = intel_mtl_port_pll_type;
|
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
v5: Few nit cleanups from rev4 (imre)
s/dev_priv/i915/ , s/c10mpllb/c10pll/ (RK)
Rebase
v6: Move the mtl code from intel_c10pll_calc_port_clock to mtl function
Fix typo in comment for REG_FIELD_PREP8 definition(Imre)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v4)
Link: https://patchwork.freedesktop.org/patch/msgid/20230413212443.1504245-4-radhakrishna.sripada@intel.com
2023-04-13 21:24:37 +00:00
|
|
|
encoder->get_config = mtl_ddi_get_config;
|
|
|
|
} else if (IS_DG2(dev_priv)) {
|
2021-07-23 17:42:35 +00:00
|
|
|
encoder->enable_clock = intel_mpllb_enable;
|
|
|
|
encoder->disable_clock = intel_mpllb_disable;
|
2021-07-23 17:42:33 +00:00
|
|
|
encoder->get_config = dg2_ddi_get_config;
|
|
|
|
} else if (IS_ALDERLAKE_S(dev_priv)) {
|
2021-02-05 21:46:31 +00:00
|
|
|
encoder->enable_clock = adls_ddi_enable_clock;
|
|
|
|
encoder->disable_clock = adls_ddi_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = adls_ddi_get_config;
|
2021-02-05 21:46:31 +00:00
|
|
|
} else if (IS_ROCKETLAKE(dev_priv)) {
|
|
|
|
encoder->enable_clock = rkl_ddi_enable_clock;
|
|
|
|
encoder->disable_clock = rkl_ddi_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = rkl_ddi_get_config;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
} else if (IS_DG1(dev_priv)) {
|
2021-02-05 21:46:25 +00:00
|
|
|
encoder->enable_clock = dg1_ddi_enable_clock;
|
|
|
|
encoder->disable_clock = dg1_ddi_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = dg1_ddi_get_config;
|
2023-08-01 13:53:38 +00:00
|
|
|
} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
if (intel_ddi_is_tc(dev_priv, port)) {
|
|
|
|
encoder->enable_clock = jsl_ddi_tc_enable_clock;
|
|
|
|
encoder->disable_clock = jsl_ddi_tc_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
|
2023-03-16 13:17:22 +00:00
|
|
|
encoder->port_pll_type = icl_ddi_tc_port_pll_type;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = icl_ddi_combo_get_config;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
} else {
|
|
|
|
encoder->enable_clock = icl_ddi_combo_enable_clock;
|
|
|
|
encoder->disable_clock = icl_ddi_combo_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = icl_ddi_combo_get_config;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
}
|
2021-03-20 04:42:42 +00:00
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 11) {
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
if (intel_ddi_is_tc(dev_priv, port)) {
|
|
|
|
encoder->enable_clock = icl_ddi_tc_enable_clock;
|
|
|
|
encoder->disable_clock = icl_ddi_tc_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
|
2023-03-16 13:17:22 +00:00
|
|
|
encoder->port_pll_type = icl_ddi_tc_port_pll_type;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = icl_ddi_tc_get_config;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
} else {
|
|
|
|
encoder->enable_clock = icl_ddi_combo_enable_clock;
|
|
|
|
encoder->disable_clock = icl_ddi_combo_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = icl_ddi_combo_get_config;
|
drm/i915: Extract icl+ .{enable,disable}_clock() vfuncs
For ICL+ we have several styles of clock routing for DDIs:
1) TC DDI + TC PHY
-> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}()
and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports()
2) ICL/TGL combo DDI + combo PHY
-> just need the stuff from icl_{map,unmap}_plls_to_ports()
3) JSL/EHL TC DDI + combo PHY
-> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and
the full combo style clock selection from icl_{map,unmap}_plls_to_ports()
4) ADLS/RKL
-> these use both TC and combo DDIs with combo PHYs, however they
always use the full combo style clock selection as per
icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all,
thus get treated the same as 2)
We extract all that from the current mess in the following way:
1) icl_ddi_tc_{enable,disable}_clock()
2) icl_ddi_combo_{enable,disable}_clock()
3) jsl_ddi_tc_{enable,disable}_clock()
4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here
v2: s/dev_priv/i915/ (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-8-ville.syrjala@linux.intel.com
2021-02-05 21:46:26 +00:00
|
|
|
}
|
2021-04-07 20:39:45 +00:00
|
|
|
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
2021-02-24 14:42:12 +00:00
|
|
|
/* BXT/GLK have fixed PLL->port mapping */
|
|
|
|
encoder->get_config = bxt_ddi_get_config;
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
} else if (DISPLAY_VER(dev_priv) == 9) {
|
2021-02-05 21:46:23 +00:00
|
|
|
encoder->enable_clock = skl_ddi_enable_clock;
|
|
|
|
encoder->disable_clock = skl_ddi_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = skl_ddi_get_config;
|
2021-02-05 21:46:23 +00:00
|
|
|
} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
|
2021-02-05 21:46:22 +00:00
|
|
|
encoder->enable_clock = hsw_ddi_enable_clock;
|
|
|
|
encoder->disable_clock = hsw_ddi_disable_clock;
|
2021-02-24 14:42:13 +00:00
|
|
|
encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
|
2021-02-24 14:42:12 +00:00
|
|
|
encoder->get_config = hsw_ddi_get_config;
|
2021-02-05 21:46:22 +00:00
|
|
|
}
|
|
|
|
|
2023-04-13 21:24:38 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 14) {
|
|
|
|
encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
|
|
|
|
} else if (IS_DG2(dev_priv)) {
|
2021-10-01 13:01:01 +00:00
|
|
|
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
|
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 12) {
|
|
|
|
if (intel_phy_is_combo(dev_priv, phy))
|
|
|
|
encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
|
|
|
|
else
|
|
|
|
encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
|
|
|
|
} else if (DISPLAY_VER(dev_priv) >= 11) {
|
|
|
|
if (intel_phy_is_combo(dev_priv, phy))
|
|
|
|
encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
|
|
|
|
else
|
|
|
|
encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
|
|
|
|
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
2021-10-01 13:01:02 +00:00
|
|
|
encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
|
2021-10-01 13:01:01 +00:00
|
|
|
} else {
|
2021-10-01 13:01:00 +00:00
|
|
|
encoder->set_signal_levels = hsw_set_signal_levels;
|
2021-10-01 13:01:01 +00:00
|
|
|
}
|
2021-10-01 13:01:00 +00:00
|
|
|
|
2021-06-08 07:35:55 +00:00
|
|
|
intel_ddi_buf_trans_init(encoder);
|
|
|
|
|
2021-05-14 15:36:53 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 13)
|
|
|
|
encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
|
|
|
|
else if (IS_DG1(dev_priv))
|
2020-10-21 08:20:29 +00:00
|
|
|
encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
|
|
|
|
else if (IS_ROCKETLAKE(dev_priv))
|
2020-06-30 21:55:59 +00:00
|
|
|
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
|
2021-03-20 04:42:42 +00:00
|
|
|
else if (DISPLAY_VER(dev_priv) >= 12)
|
2020-06-30 21:55:59 +00:00
|
|
|
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
|
2023-08-01 13:53:38 +00:00
|
|
|
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
|
2020-06-30 21:55:59 +00:00
|
|
|
encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
else if (DISPLAY_VER(dev_priv) == 11)
|
2020-06-30 21:55:59 +00:00
|
|
|
encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
|
drm/i915/display: rename display version macros
While converting the rest of the driver to use GRAPHICS_VER() and
MEDIA_VER(), following what was done for display, some discussions went
back on what we did for display:
1) Why is the == comparison special that deserves a separate
macro instead of just getting the version and comparing directly
like is done for >, >=, <=?
2) IS_DISPLAY_RANGE() is weird in that it omits the "_VER" for
brevity. If we remove the current users of IS_DISPLAY_VER(), we
could actually repurpose it for a range check
With (1) there could be an advantage if we used gen_mask since multiple
conditionals be combined by the compiler in a single and instruction and
check the result. However a) INTEL_GEN() doesn't use the mask since it
would make the code bigger everywhere else and b) in the cases it made
sense, it also made sense to convert to the _RANGE() variant.
So here we repurpose IS_DISPLAY_VER() to work with a [ from, to ] range
like was the IS_DISPLAY_RANGE() and convert the current IS_DISPLAY_VER()
users to use == and != operators. Aside from the definition changes,
this was done by the following semantic patch:
@@ expression dev_priv, E1; @@
- !IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) != E1
@@ expression dev_priv, E1; @@
- IS_DISPLAY_VER(dev_priv, E1)
+ DISPLAY_VER(dev_priv) == E1
@@ expression dev_priv, from, until; @@
- IS_DISPLAY_RANGE(dev_priv, from, until)
+ IS_DISPLAY_VER(dev_priv, from, until)
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
[Jani: Minor conflict resolve while applying.]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210413051002.92589-4-lucas.demarchi@intel.com
2021-04-13 05:09:53 +00:00
|
|
|
else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
|
2021-02-09 19:16:28 +00:00
|
|
|
encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
|
2020-06-30 21:55:59 +00:00
|
|
|
else
|
|
|
|
encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11)
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->saved_port_bits =
|
|
|
|
intel_de_read(dev_priv, DDI_BUF_CTL(port))
|
|
|
|
& DDI_BUF_PORT_REVERSAL;
|
2018-03-06 10:41:55 +00:00
|
|
|
else
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->saved_port_bits =
|
|
|
|
intel_de_read(dev_priv, DDI_BUF_CTL(port))
|
|
|
|
& (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
|
2019-11-06 07:17:17 +00:00
|
|
|
|
2023-02-08 01:55:02 +00:00
|
|
|
if (intel_bios_encoder_lane_reversal(devdata))
|
2021-02-11 11:42:09 +00:00
|
|
|
dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->dp.output_reg = INVALID_MMIO_REG;
|
|
|
|
dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
|
2023-06-30 15:58:42 +00:00
|
|
|
|
2023-06-30 15:58:44 +00:00
|
|
|
if (need_aux_ch(encoder, init_dp)) {
|
2023-06-30 15:58:42 +00:00
|
|
|
dig_port->aux_ch = intel_dp_aux_ch(encoder);
|
2023-06-30 15:58:44 +00:00
|
|
|
if (dig_port->aux_ch == AUX_CH_NONE)
|
|
|
|
goto err;
|
|
|
|
}
|
2012-10-26 21:05:52 +00:00
|
|
|
|
2019-07-09 18:39:33 +00:00
|
|
|
if (intel_phy_is_tc(dev_priv, phy)) {
|
2020-01-17 14:29:27 +00:00
|
|
|
bool is_legacy =
|
2021-03-17 16:36:52 +00:00
|
|
|
!intel_bios_encoder_supports_typec_usb(devdata) &&
|
|
|
|
!intel_bios_encoder_supports_tbt(devdata);
|
2019-06-28 14:36:20 +00:00
|
|
|
|
2023-03-21 22:00:59 +00:00
|
|
|
if (!is_legacy && init_hdmi) {
|
|
|
|
is_legacy = !init_dp;
|
|
|
|
|
|
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
|
|
"VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
|
|
|
|
port_name(port),
|
|
|
|
str_yes_no(init_dp),
|
|
|
|
is_legacy ? "legacy" : "non-legacy");
|
|
|
|
}
|
|
|
|
|
2023-05-12 19:55:12 +00:00
|
|
|
encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
|
|
|
|
encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
|
|
|
|
|
2023-03-23 14:20:13 +00:00
|
|
|
if (intel_tc_port_init(dig_port, is_legacy) < 0)
|
|
|
|
goto err;
|
2019-06-28 14:36:20 +00:00
|
|
|
}
|
2018-12-14 18:27:02 +00:00
|
|
|
|
drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available
drm specific WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.
Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device or drm_i915_private struct
pointer is readily available.
The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.
@rule1@
identifier func, T;
@@
func(...) {
...
struct drm_device *T = ...;
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule2@
identifier func, T;
@@
func(struct drm_device *T,...) {
<...
(
-WARN(
+drm_WARN(T,
...)
|
-WARN_ON(
+drm_WARN_ON(T,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(T,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(T,
...)
)
...>
}
@rule3@
identifier func, T;
@@
func(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
@rule4@
identifier func, T;
@@
func(struct drm_i915_private *T,...) {
<+...
(
-WARN(
+drm_WARN(&T->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&T->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&T->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&T->drm,
...)
)
...+>
}
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-3-pankaj.laxminarayan.bharadiya@intel.com
2020-02-20 16:55:01 +00:00
|
|
|
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
|
2022-04-14 21:06:53 +00:00
|
|
|
dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
|
2017-02-24 14:19:59 +00:00
|
|
|
|
2021-03-20 04:42:42 +00:00
|
|
|
if (DISPLAY_VER(dev_priv) >= 11) {
|
2020-03-11 15:54:20 +00:00
|
|
|
if (intel_phy_is_tc(dev_priv, phy))
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = intel_tc_port_connected;
|
2020-03-11 15:54:20 +00:00
|
|
|
else
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = lpt_digital_port_connected;
|
2023-03-02 16:10:08 +00:00
|
|
|
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
|
|
|
|
dig_port->connected = bdw_digital_port_connected;
|
|
|
|
} else if (DISPLAY_VER(dev_priv) == 9) {
|
|
|
|
dig_port->connected = lpt_digital_port_connected;
|
|
|
|
} else if (IS_BROADWELL(dev_priv)) {
|
|
|
|
if (port == PORT_A)
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = bdw_digital_port_connected;
|
2020-03-11 15:54:20 +00:00
|
|
|
else
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = lpt_digital_port_connected;
|
2023-03-02 16:10:08 +00:00
|
|
|
} else if (IS_HASWELL(dev_priv)) {
|
2020-03-11 15:54:22 +00:00
|
|
|
if (port == PORT_A)
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = hsw_digital_port_connected;
|
2020-03-11 15:54:20 +00:00
|
|
|
else
|
2020-07-01 04:50:54 +00:00
|
|
|
dig_port->connected = lpt_digital_port_connected;
|
2020-03-11 15:54:20 +00:00
|
|
|
}
|
|
|
|
|
2020-07-01 04:50:54 +00:00
|
|
|
intel_infoframe_init(dig_port);
|
2018-12-14 18:27:02 +00:00
|
|
|
|
2023-03-02 16:10:07 +00:00
|
|
|
if (init_dp) {
|
|
|
|
if (!intel_ddi_init_dp_connector(dig_port))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
dig_port->hpd_pulse = intel_dp_hpd_pulse;
|
|
|
|
|
|
|
|
if (dig_port->dp.mso_link_count)
|
|
|
|
encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* In theory we don't need the encoder->type check,
|
|
|
|
* but leave it just in case we have some really bad VBTs...
|
|
|
|
*/
|
|
|
|
if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
|
|
|
|
if (!intel_ddi_init_hdmi_connector(dig_port))
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2014-08-04 06:15:09 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
2019-11-06 07:17:17 +00:00
|
|
|
drm_encoder_cleanup(&encoder->base);
|
2020-07-01 04:50:54 +00:00
|
|
|
kfree(dig_port);
|
2012-10-26 21:05:52 +00:00
|
|
|
}
|